Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
1023
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
46.4
Functional Description
The Secure Hash Algorithm (SHA) module requires a padded message according to FIPS180-2 specification. The first
block of the message must be indicated to the module by a specific command. The SHA module produces a N-bit
message digest each time a block is written and processing period ends. N is 160 for SHA1, 224 for SHA224, 256 for
SHA256.
block of the message must be indicated to the module by a specific command. The SHA module produces a N-bit
message digest each time a block is written and processing period ends. N is 160 for SHA1, 224 for SHA224, 256 for
SHA256.
46.4.1 SHA
Algorithm
The module can process SHA1, SHA224, SHA256, by means of a configuration field in the SHA_MR register.
46.4.2 Processing
Period
The processing period can be configured.
The short processing period allows to allocate bandwidth to the SHA module whereas the long processing period
allocates more bandwidth on the system bus to other applications (example: DMA channels not associated with SHA).
allocates more bandwidth on the system bus to other applications (example: DMA channels not associated with SHA).
In SHA1 mode, the shortest processing period is 85 clock cycles + 2 clock cycles for start command synchronization. The
longest period is 209 clock cycles + 2 clock cycles.
longest period is 209 clock cycles + 2 clock cycles.
In SHA256 and SHA224 mode, the shortest processing period is 72 clock cycles + 2 clock cycles for start command
synchronization. The longest period is 194 clock cycles + 2 clock cycles.
synchronization. The longest period is 194 clock cycles + 2 clock cycles.
46.4.3 Double
Input
Buffer
The input data register can be double-buffered to reduce the runtime of large files.
This mode allows to write a new message block while the previous message block is being processed. This is only
possible when DMA accesses are performed (SMOD=0x2).
possible when DMA accesses are performed (SMOD=0x2).
The DUALBUFF field in SHA_MR register must be set to 1 to get access to double buffer.
46.4.4 Start
Modes
The SMOD field in the SHA Mode Register (SHA_MR) is used to select the hash processing start mode.
46.4.4.1 Manual Mode
The sequence is as follows:
Set the bit DATRDY (Data Ready) in the SHA Interrupt Enable Register (SHA_IER), depending on whether an
interrupt is required or not at the end of processing.
interrupt is required or not at the end of processing.
For the first block of a message, the FIRST command must be set by writing a 1 into the corresponding bit of the
Control Register (SHA_CR). For the other blocks, there is nothing to write in this Control Register.
Control Register (SHA_CR). For the other blocks, there is nothing to write in this Control Register.
Write the block to be processed in the Input Data Registers.
Set the START bit in the SHA Control Register SHA_CR to begin the processing.
When the processing completes, the bit DATRDY in the SHA Interrupt Status Register (SHA_ISR) raises. If an
interrupt has been enabled by setting the bit DATRDY in SHA_IER, the interrupt line of the SHA is activated.
interrupt has been enabled by setting the bit DATRDY in SHA_IER, the interrupt line of the SHA is activated.
Repeat the write procedure for each block, start procedure and wait for the interrupt procedure up to the last block
of the entire message. Each time the start procedure is complete, the DATRDY flag is cleared.
of the entire message. Each time the start procedure is complete, the DATRDY flag is cleared.
After the last block is processed (DATRDY flag is set, if an interrupt has been enabled by setting the bit DATRDY
in SHA_IER, the interrupt line of the SHA is activated), read the message digest in the Output Data Registers. The
DATRDY flag is automatically cleared when reading the SHA_ODATARx registers.
in SHA_IER, the interrupt line of the SHA is activated), read the message digest in the Output Data Registers. The
DATRDY flag is automatically cleared when reading the SHA_ODATARx registers.