Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
1052
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
48.8
PLL Characteristics
The following configuration of ICPLLA and OUTA must be done for each PLLA frequency range.
48.9
I/Os
Criteria used to define the maximum frequency of the I/Os:
Output duty cycle (40%-60%)
Minimum output swing: 100 mV to VDDIO - 100 mV
Addition of rising and falling time inferior to 75% of the period
Notes: 1.
3.3V domain: V
VDDIOP
from 3.0V to 3.6V, maximum external capacitor = 40 pF
2.
1.8V domain: V
VDDIOP
from 1.65V to 1.95V, maximum external capacitor = 20 pF
Table 48-15. PLLA Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
F
OUT
Output Frequency
Refer to following table
400
800
MHz
F
IN
Input Frequency
2
32
MHz
I
PLL
Current Consumption
active mode
3.6
4.5
mA
standby mode
1
µA
T
Startup Time
50
µs
Table 48-16. PLLA Frequency Regarding ICPLLA and OUTA
PLL Frequency Range (MHz)
ICPLLA
OUTA
745 - 800
0
0
0
695 - 750
0
0
1
645 - 700
0
1
0
595 - 650
0
1
1
545 - 600
1
0
0
495 - 550
1
0
1
445 - 500
1
1
0
400 - 450
1
1
1
Table 48-17. I/O Characteristics
Symbol
Parameter
Conditions
Min
Max
Units
FreqMax
VDDIOP powered Pins frequency
66
MHz
1.8V domain
66
MHz