Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
1053
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
48.10 Analog-to-Digital Converter (ADC)
Note:
1. The Track-and-Hold Acquisition Time is given by:
The ADC internal clock is divided by 2 in order to generate a clock with a duty cycle of 75%. So the maximum conver-
sion time is give by:
sion time is give by:
The full speed is obtained for an input source impedance of < 50 Ohms maximum, or TTH = 500 ns.
In order to make the TSADC work properly, the SHTIM field in TSADCC Mode Register is to be calculated according
to this Track and Hold Acquisition Time, also called Sampled and Hold Time.
In order to make the TSADC work properly, the SHTIM field in TSADCC Mode Register is to be calculated according
to this Track and Hold Acquisition Time, also called Sampled and Hold Time.
Table 48-18. Channel Conversion Time and ADC Clock
Parameter
Conditions
Min
Typ
Max
Units
ADC Clock Frequency
10-bit resolution mode
13.2
MHz
Startup Time
Return from Idle Mode
40
µs
Track and Hold Acquisition Time (TTH)
ADC Clock = 13.2 MHz
0.5
µs
Conversion Time (TCT)
ADC Clock = 13.2 MHz
ADC Clock = 5 MHz
1.74
4.6
µs
Throughput Rate
ADC Clock = 13.2 MHz
ADC Clock = 5 MHz
440
192
kSPS
Table 48-19. External Voltage Reference Input
Parameter
Conditions
Min
Typ
Max
Units
ADVREF Input Voltage Range
2.4
VDDANA
V
ADVREF Average Current
600
µA
Current Consumption on VDDANA
600
µA
TTH (ns)
500
0.12
Z
IN
×
(
) Ω
( )
+
=
TCT µs
( )
23
Fclk
-----------
MHz
(
)
=
Table 48-20. Analog Inputs
Parameter
Min
Typ
Max
Units
Input Voltage Range
0
ADVREF
V
Input Peak Current
2.5
mA
Input Capacitance
7
10
pF
Input Impedance
50
Ohms