Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
1055
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
48.12 Core Power Supply POR Characteristics
48.12.1 Power Sequence Requirements
The AT91 board design must comply with the power-up guidelines below to guarantee reliable operation of the device.
Any deviation from these sequences may prevent the device from booting.
48.12.2 Power-Up Sequence
Figure 48-4. VDDCORE and VDDIO Constraints at Startup
VDDCORE and VDDBU are controlled by internal POR (Power-On-Reset) to guarantee that these power sources reach
their target values prior to the release of POR.
their target values prior to the release of POR.
VDDIOP must be
≥ V
ih
(refer to DC characteristics,
, for more details), (Tres + T1) at the latest, after
VDDCORE has reached
V
th+
.
VDDIOM must reach V
oh
(refer to DC characteristics,
, for more details), (Tres +T1 +T2) at the latest,
after VDDCORE has reached
V
th+
T
RES
is a POR characteristic
T1 = 3 x T
SLCK
T2 = 16 x T
SLCK
Table 48-23. Power-On-Reset Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
th+
Threshold Voltage Rising
Minimum Slope of +2.0V/30ms
0.5
0.7
0.89
V
V
th-
Threshold Voltage Falling
0.4
0.6
0.85
V
T
RES
Reset Time
30
70
130
µs
Idd
Current consumption
After T
RES
3
7
µA
VDD (V)
Core Supply POR Output
VDDIOtyp
Vih
Vth+
t
SLCK
<--- Tres --->
VDDIO > Vih
VDDCORE
VDDIO
< T1 >
VDDCOREtyp
Voh
VDDIO > Voh
<------------ T2----------->