Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

180

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

1.

Enabling the 12 MHz Main Oscillator:

The main oscillator is enabled by setting the MOSCEN field in the CKGR_MOR register. In some cases it may be 
advantageous to define a start-up time. This can be achieved by writing a value in the OSCOUNT field in the 
CKGR_MOR register.

Once this register has been correctly configured, the user must wait for MOSCS field in the PMC_SR register to be 
set. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associ-
ated interrupt to MOSCS has been enabled in the PMC_IER register.

2.

Setting PLLA and divider:

All parameters needed to configure PLLA and the divider are located in the CKGR_PLLAR register.

The DIVA field is used to control the divider itself. A value between 0 and 255 can be programmed. Divider output 
is divider input divided by DIVA parameter. By default DIVA parameter is set to 0 which means that divider is 
turned off.

The OUTA field is used to select the PLLA output frequency range.

The MULA field is the PLLA multiplier factor. This parameter can be programmed between 0 and 254. If MULA is 
set to 0, PLLA will be turned off, otherwise the PLLA output frequency is PLLA input frequency multiplied by 
(MULA + 1).

The PLLACOUNT field specifies the number of slow clock cycles before LOCKA bit is set in the PMC_SR register 
after CKGR_PLLAR register has been written.

Once the PMC_PLLAR register has been written, the user must wait for the LOCKA bit to be set in the PMC_SR 
register. This can be done either by polling the status register or by waiting the interrupt line to be raised if the 
associated interrupt to LOCKA has been enabled in the PMC_IER register. All parameters in CKGR_PLLAR can 
be programmed in a single write operation. If at some stage one of the following parameters, MULA, DIVA is mod-
ified, LOCKA bit will go low to indicate that PLLA is not ready yet. When PLLA is locked, LOCKA will be set again. 
The user is constrained to wait for LOCKA bit to be set before using the PLLA output clock.

Code Example: 

write_register(CKGR_PLLAR,0x00040805)

If PLLA and divider are enabled, the PLLA input clock is the main clock. PLLA output clock is PLLA input clock 
multiplied by 5. Once CKGR_PLLAR has been written, LOCKA bit will be set after eight slow clock cycles.

3.

Setting PLL B and divider B:

All parameters needed to configure PLL B and divider B are located in the CKGR_PLLBR register.

The DIVB field is used to control divider B itself. A value between 0 and 255 can be programmed. Divider B output 
is divider B input divided by DIVB parameter. By default DIVB parameter is set to 0 which means that divider B is 
turned off.

The OUTB field is used to select the PLL B output frequency range.

The MULB field is the PLL B multiplier factor. This parameter can be programmed between 0 and 2047. If MULB is 
set to 0, PLL B will be turned off, otherwise the PLL B output frequency is PLL B input frequency multiplied by 
(MULB + 1).

The PLLBCOUNT field specifies the number of slow clock cycles before LOCKB bit is set in the PMC_SR register 
after CKGR_PLLBR register has been written.

Once the PMC_PLLB register has been written, the user must wait for the LOCKB bit to be set in the PMC_SR 
register. This can be done either by polling the status register or by waiting the interrupt line to be raised if the 
associated interrupt to LOCKB has been enabled in the PMC_IER register. All parameters in CKGR_PLLBR can 
be programmed in a single write operation. If at some stage one of the following parameters, MULB, DIVB is mod-
ified, LOCKB bit will go low to indicate that PLL B is not ready yet. When PLL B is locked, LOCKB will be set again. 
The user is constrained to wait for LOCKB bit to be set before using the PLL A output clock.

The USBDIV field is used to control the additional divider by 1, 2 or 4, which generates the USB clock(s).