Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The Power Management Controller controls the clocks of each embedded peripheral by means of the Peripheral Clock
Controller. The user can individually enable and disable the clock on the peripherals and select a division factor from
MCK. This is done through the Peripheral Control Register (PMC_PCR).

In order to save power consumption, the division factor can be 1, 2, 4 or 8. PMC_PCR is a register that features a
command and acts like a mailbox. To write the division factor on a particular peripheral, the user needs to write a WRITE
command, the peripheral ID and the chosen division factor. To read the current division factor on a particular peripheral,
the user just needs to write the READ command and the peripheral ID.

Code Example to select divider 8 for peripheral 2 and enable its clock: 

write_register(PMC_PCR,0x10031002)

Code Example to read the divider of peripheral 4: 

write_register(PMC_PCR,0x00000004)

When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically disabled
after a reset.

In order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last
programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the system.

The bit number within the Peripheral Control registers is the Peripheral Identifier defined at the product level. Generally,
the bit number corresponds to the interrupt source number assigned to the peripheral.

The PMC controls 2 signals to be output on external pins PCKx. Each signal can be independently programmed via the
PMC_PCKx registers.

PCKx can be independently selected between the Slow clock, the Master Clock, the PLLACK/PLLADIV2, the UTMI PLL
output and the main clock by writing the CSS field in PMC_PCKx. Each output signal can also be divided by a power of 2
between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx. 

Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of PMC_SCER and
PMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCKx bits of PMC_SCSR
(System Clock Status Register).

Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actually what has been
programmed in the Programmable Clock registers.

As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly
recommended to disable the Programmable Clock before any configuration change and to re-enable it after the change
is actually performed.