Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
178
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
22.5
Processor Clock Controller
The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle Mode. The Processor Clock
can be disabled by writing the System Clock Disable Register (PMC_SCDR). The status of this clock (at least for debug
purposes) can be read in the System Clock Status Register (PMC_SCSR).
can be disabled by writing the System Clock Disable Register (PMC_SCDR). The status of this clock (at least for debug
purposes) can be read in the System Clock Status Register (PMC_SCSR).
The Processor Clock (PCK) is enabled after a reset and is automatically re-enabled by any enabled interrupt.
The Processor Idle Mode is achieved by disabling the Processor Clock and entering Wait for Interrupt Mode.
The Processor Clock is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product.
Note: The ARM Wait for Interrupt mode is entered by a CP15 coprocessor operation. Refer to the Atmel application note,
O p t i m i z i n g P o w e r C o n s u m p t i o n f o r A T 9 1 S A M 9 2 6 1 - b a s e d S y s t e m s , l i t . n u m b e r 6 2 1 7 .
(
The Processor Idle Mode is achieved by disabling the Processor Clock and entering Wait for Interrupt Mode.
The Processor Clock is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product.
Note: The ARM Wait for Interrupt mode is entered by a CP15 coprocessor operation. Refer to the Atmel application note,
O p t i m i z i n g P o w e r C o n s u m p t i o n f o r A T 9 1 S A M 9 2 6 1 - b a s e d S y s t e m s , l i t . n u m b e r 6 2 1 7 .
(
http://www.atmel.com/dyn/resources/prod_documents/doc6217.pdf
) When the Processor Clock is disabled, the current
instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the
system bus.
system bus.
22.6
USB Device and Host Clocks
The USB Source Clock is always generated from the PLL B output. If using the USB, the user must program the PLL to
generate a 48 MHz, a 96 MHz or a 192 MHz signal with an accuracy of ± 0.25% depending on the USBDIV bit in
CKGR_PLLBR.
generate a 48 MHz, a 96 MHz or a 192 MHz signal with an accuracy of ± 0.25% depending on the USBDIV bit in
CKGR_PLLBR.
When the PLL B output is stable, i.e., the LOCKB is set:
The USB host clock can be enabled by setting the UHP bit in PMC_SCER. To save power on this peripheral when it is
not used, the user can set the UHP bit in PMC_SCDR. The UHP bit in PMC_SCSR gives the activity of this clock. The
USB host port require both the 12/48 MHz signal and the Master Clock. The Master Clock may be controlled via the
Master Clock Controller.
not used, the user can set the UHP bit in PMC_SCDR. The UHP bit in PMC_SCSR gives the activity of this clock. The
USB host port require both the 12/48 MHz signal and the Master Clock. The Master Clock may be controlled via the
Master Clock Controller.
The USB device clock can be enabled by setting the UDP bit in PMC_SCER. To save power on this peripheral when it is
not used, the user can set the UDP bit in PMC_SCDR. The UDP bit in PMC_SCSR gives the activity of this clock. The
USB device port require both the 48 MHz signal and the Master Clock. The Master Clock may be controlled via the
Master Clock Controller.
not used, the user can set the UDP bit in PMC_SCDR. The UDP bit in PMC_SCSR gives the activity of this clock. The
USB device port require both the 48 MHz signal and the Master Clock. The Master Clock may be controlled via the
Master Clock Controller.
Figure 22-2. USB Clock Controller
22.7
LP-DDR/DDR2 Clock
The Power Management Controller controls the clocks of the DDR memory.
The DDR clock can be enabled and disabled with DDRCK bit respectively in PMC_SCER and PMC_SDER registers. At
reset DDR clock is disabled to save power consumption.
reset DDR clock is disabled to save power consumption.
In the case MDIV = ‘00’, (PCK = MCK) and DDRCK clock is not available.
If Input clock is PLLACK/PLLADIV2 the DDR Controller can drive DDR2 and LP-DDR at up to 133MHz with MDIV = ‘11’.
To save PLLA power consumption, the user can choose UPLLCK an Input clock for the system. In this case the DDR
Controller can drive LD-DDR at up to 120MHz.
Controller can drive LD-DDR at up to 120MHz.
USB
Source
Clock
UDP Clock (UDPCK)
UDP
USBDIV
Divider
/1,/2,/4
UHP Clock (UHPCK)
UHP