Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
384
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
30.9.4 Write
Mode
The WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal
controls the write operation.
controls the write operation.
30.9.4.1 Write is Controlled by NWE (WRITE_MODE = 1)
shows the waveforms of a write operation with WRITE_MODE set to 1. The data is put on the bus during
the pulse and hold steps of the NWE signal. The internal data buffers are switched to output mode after the
NWE_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NCS.
NWE_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NCS.
Figure 30-14. WRITE_MODE = 1. The write operation is controlled by NWE
30.9.4.2 Write is Controlled by NCS (WRITE_MODE = 0)
shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus during
the pulse and hold steps of the NCS signal. The internal data buffers are switched to output mode after the
NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE.
NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE.
Figure 30-15. WRITE_MODE = 0. The write operation is controlled by NCS
MCK
D[31:0]
NCS
A
[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NBS2, NBS3,
A0, A1
NWE,
NWR0, NWR1,
NWR2, NWR3
NWR2, NWR3
MCK
D[31:0]
NCS
NWE,
NWR0, NWR1,
NWR2, NWR3
NWR2, NWR3
A
[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NBS2, NBS3,
A0, A1