Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

386

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

For write operations:

If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address, byte select lines, and
NCS signal after the rising edge of NWE. This is true for WRITE_MODE = 1 only. See 

For read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable behavior.

In read and write cycles, the setup and hold time parameters are defined in reference to the address bus. For external
devices that require setup and hold time between NCS and NRD signals (read), or between NCS and NWE signals
(write), these setup and hold times must be converted into setup and hold times in reference to the address bus.

Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention or
operation conflict.

The SMC always inserts an idle cycle between 2 transfers on separate chip selects. This idle cycle ensures that there is
no bus contention between the de-activation of one device and the activation of the next one. 

During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to NWR3, NCS[0..5], NRD lines
are all set to 1.

 illustrates a chip select wait state between access on Chip Select 0 and Chip Select 2.

A[25:2]

NBS0, NBS1,
NBS2, NBS3,
A0,A1

NCS0

NRD_CYCLE

Chip Select

Wait State

NWE_CYCLE

MCK

NCS2

NRD

NWE

D[31:0]

Read to Write

Wait State