Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
385
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
30.9.5 Write
Protected
Registers
To prevent any single software error that may corrupt SMC behavior, the registers listed below can be write protected by
setting the WPEN bit in the SMC Write Protect Mode Register (SMC_WPMR).
setting the WPEN bit in the SMC Write Protect Mode Register (SMC_WPMR).
If a write access in a write protected register is detected, then the WPVS flag in the SMC Write Protect Status Register
(SMC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
(SMC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is automatically reset after reading the SMC Write Protect Status Register (SMC_WPSR).
The write protected registers are:
30.9.6 Coding Timing Parameters
All timing parameters are defined for one chip select and are grouped together in one SMC_REGISTER according to
their type.
their type.
The SMC_SETUP register groups the definition of all setup parameters:
NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP
The SMC_PULSE register groups the definition of all pulse parameters:
NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE
The SMC_CYCLE register groups the definition of all cycle parameters:
NRD_CYCLE, NWE_CYCLE
shows how the timing parameters are coded and their permitted range.
30.9.7 Reset Values of Timing Parameters
gives the default value of timing parameters at reset.
30.9.8 Usage
Restriction
The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP and PULSE parameters
is larger than the corresponding CYCLE parameter, this leads to unpredictable behavior of the SMC.
is larger than the corresponding CYCLE parameter, this leads to unpredictable behavior of the SMC.
For read operations:
Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the memory interface
because of the propagation delay of theses signals through external logic and pads. If positive setup and hold values
must be verified, then it is strictly recommended to program non-null values so as to cover possible skews between
address, NCS and NRD signals.
because of the propagation delay of theses signals through external logic and pads. If positive setup and hold values
must be verified, then it is strictly recommended to program non-null values so as to cover possible skews between
address, NCS and NRD signals.
Table 30-4. Coding and Range of Timing Parameters
Coded Value
Number of Bits
Effective Value
Permitted Range
Coded Value
Effective Value
setup [5:0]
6
128 x setup[5] + setup[4:0]
0
≤ ≤ 31
0
≤ ≤ 128+31
pulse [6:0]
7
256 x pulse[6] + pulse[5:0]
0
≤ ≤ 63
0
≤ ≤ 256+63
cycle [8:0]
9
256 x cycle[8:7] + cycle[6:0]
0
≤ ≤ 127
0
≤ ≤ 256+127
0
≤ ≤ 512+127
0
≤ ≤ 768+127