Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

387

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write
cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait
state. The early read cycle thus only occurs between a write and read access to the same memory device (same chip
select).

An early read wait state is automatically inserted if at least one of the following conditions is valid:



if the write controlling signal has no hold time and the read controlling signal has no setup time (

).



in NCS write controlled mode (WRITE_MODE = 0), if there is no hold timing on the NCS signal and the 
NCS_RD_SETUP parameter is set to 0, regardless of the read mode (

). The write operation must end 

with a NCS rising edge. Without an Early Read Wait State, the write operation could not complete properly.



in NWE controlled mode (WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD = 0), the feedback of the 
write control signal is used to control address, data, chip select and byte select lines. If the external write control 
signal is not inactivated as expected due to load capacitances, an Early Read Wait State is inserted and address, 
data and control signals are maintained one more cycle. See 

write cycle

Early Read

wait state

MCK

NRD

NWE

read cycle

no setup

no hold

D[31:0]

NBS0, NBS1,
NBS2, NBS3,
A0, A1

A[25:2]