Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
39
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD,
QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve DSP operations.
The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by an MSR instruction
writing to the CPSR. Instructions cannot execute conditionally on the status of the Q flag.
QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve DSP operations.
The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by an MSR instruction
writing to the CPSR. Instructions cannot execute conditionally on the status of the Q flag.
The J bit in the CPSR indicates when the ARM9EJ-S core is in Jazelle state, where:
J = 0: The processor is in ARM or Thumb state, depending on the T bit
J = 1: The processor is in Jazelle state.
Mode: five bits to encode the current processor mode
9.4.8 Exceptions
9.4.8.1 Exception Types and Priorities
The
ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privileged mode. The types of
exceptions are:
Fast interrupt (FIQ)
Normal interrupt (IRQ)
Data and Prefetched aborts (Abort)
Undefined instruction (Undefined)
Software interrupt and Reset (Supervisor)
When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the state.
More than one exception can happen at a time, therefore the ARM9EJ-S takes the arisen exceptions according to the
following priority order:
following priority order:
Reset (highest priority)
Data Abort
FIQ
IRQ
Prefetch Abort
BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority)
The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive.
Note that there is one exception in the priority scheme: when FIQs are enabled and a Data Abort occurs at the same time
as an FIQ, the ARM9EJ-S core enters the Data Abort handler, and proceeds immediately to FIQ vector. A normal return
from the FIQ causes the Data Abort handler to resume execution. Data Aborts must have higher priority than FIQs to
ensure that the transfer error does not escape detection.
as an FIQ, the ARM9EJ-S core enters the Data Abort handler, and proceeds immediately to FIQ vector. A normal return
from the FIQ causes the Data Abort handler to resume execution. Data Aborts must have higher priority than FIQs to
ensure that the transfer error does not escape detection.
9.4.8.2 Exception Modes and Handling
Exceptions arise whenever the normal flow of a program must be halted temporarily, for example, to service an interrupt
from a peripheral.
from a peripheral.
When handling an ARM exception, the ARM9EJ-S core performs the following operations:
1.
Preserves the address of the next instruction in the appropriate Link Register that corresponds to the new mode
that has been entered. When the exception entry is from:
that has been entered. When the exception entry is from:
ARM and Jazelle states, the ARM9EJ-S copies the address of the next instruction into LR (current PC(r15)
+ 4 or PC + 8 depending on the exception).
+ 4 or PC + 8 depending on the exception).
THUMB state, the ARM9EJ-S writes the value of the PC into LR, offset by a value (current PC + 2, PC + 4
or PC + 8 depending on the exception) that causes the program to resume from the correct place on return.
or PC + 8 depending on the exception) that causes the program to resume from the correct place on return.
2.
Copies the CPSR into the appropriate SPSR.
3.
Forces the CPSR mode bits to a value that depends on the exception.
4.
Forces the PC to fetch the next instruction from the relevant exception vector.
The register r13 is also banked across exception modes to provide each exception handler with private stack pointer.