Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
40
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
The ARM9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions.
When an exception has completed, the exception handler must move both the return value in the banked LR minus an
offset to the PC and the SPSR to the CPSR. The offset value varies according to the type of exception. This action
restores both PC and the CPSR.
offset to the PC and the SPSR to the CPSR. The offset value varies according to the type of exception. This action
restores both PC and the CPSR.
The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the requirement for
register saving which minimizes the overhead of context switching.
register saving which minimizes the overhead of context switching.
The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be completed. When a
Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as invalid, but does not take the exception until
the instruction reaches the Execute stage in the pipeline. If the instruction is not executed, for example because a branch
occurs while it is in the pipeline, the abort does not take place.
Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as invalid, but does not take the exception until
the instruction reaches the Execute stage in the pipeline. If the instruction is not executed, for example because a branch
occurs while it is in the pipeline, the abort does not take place.
The breakpoint (BKPT) instruction is a new feature of ARM9EJ-S that is destined to solve the problem of the Prefetch
Abort. A breakpoint instruction operates as though the instruction caused a Prefetch Abort.
A breakpoint instruction does not cause the ARM9EJ-S to take the Prefetch Abort exception until the instruction reaches
the Execute stage of the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the
pipeline, the breakpoint does not take place.
Abort. A breakpoint instruction operates as though the instruction caused a Prefetch Abort.
A breakpoint instruction does not cause the ARM9EJ-S to take the Prefetch Abort exception until the instruction reaches
the Execute stage of the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the
pipeline, the breakpoint does not take place.
9.4.9
ARM Instruction Set Overview
The ARM instruction set is divided into:
Branch instructions
Data processing instructions
Status register transfer instructions
Load and Store instructions
Coprocessor instructions
Exception-generating instructions
ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]).
gives the ARM instruction mnemonic list.
Table 9-2.
ARM Instruction Mnemonic List
Mnemonic
Operation
Mnemonic
Operation
MOV
Move
MVN
Move Not
ADD
Add
ADC
Add with Carry
SUB
Subtract
SBC
Subtract with Carry
RSB
Reverse Subtract
RSC
Reverse Subtract with Carry
CMP
Compare
CMN
Compare Negated
TST
Test
TEQ
Test Equivalence
AND
Logical AND
BIC
Bit Clear
EOR
Logical Exclusive OR
ORR
Logical (inclusive) OR
MUL
Multiply
MLA
Multiply Accumulate
SMULL
Sign Long Multiply
UMULL
Unsigned Long Multiply
SMLAL
Signed Long Multiply
Accumulate
Accumulate
UMLAL
Unsigned Long Multiply
Accumulate
Accumulate
MSR
Move to Status Register
MRS
Move From Status Register
B
Branch
BL
Branch and Link
BX
Branch and Exchange
SWI
Software Interrupt
LDR
Load Word
STR
Store Word