Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
41
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
9.4.10 New ARM Instruction Set
.
Notes: 1.
A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles.
LDRSH
Load Signed Halfword
LDRSB
Load Signed Byte
LDRH
Load Half Word
STRH
Store Half Word
LDRB
Load Byte
STRB
Store Byte
LDRBT
Load Register Byte with
Translation
Translation
STRBT
Store Register Byte with
Translation
Translation
LDRT
Load Register with
Translation
Translation
STRT
Store Register with
Translation
Translation
LDM
Load Multiple
STM
Store Multiple
SWP
Swap Word
SWPB
Swap Byte
MCR
Move To Coprocessor
MRC
Move From Coprocessor
LDC
Load To Coprocessor
STC
Store From Coprocessor
CDP
Coprocessor Data
Processing
Processing
Table 9-2.
ARM Instruction Mnemonic List (Continued)
Mnemonic
Operation
Mnemonic
Operation
Table 9-3.
New ARM Instruction Mnemonic List
Mnemonic
Operation
Mnemonic
Operation
BXJ
Branch and exchange to
Java
Java
MRRC
Move double from
coprocessor
coprocessor
BLX
Branch, Link and exchange
MCR2
Alternative move of ARM reg
to coprocessor
to coprocessor
SMLAxy
Signed Multiply Accumulate
16 * 16 bit
16 * 16 bit
MCRR
Move double to coprocessor
SMLAL
Signed Multiply Accumulate
Long
Long
CDP2
Alternative Coprocessor
Data Processing
Data Processing
SMLAWy
Signed Multiply Accumulate
32 * 16 bit
32 * 16 bit
BKPT
Breakpoint
SMULxy
Signed Multiply 16 * 16 bit
PLD
Soft Preload, Memory
prepare to load from address
prepare to load from address
SMULWy
Signed Multiply 32 * 16 bit
STRD
Store Double
QADD
Saturated Add
STC2
Alternative Store from
Coprocessor
Coprocessor
QDADD
Saturated Add with Double
LDRD
Load Double
QSUB
Saturated subtract
LDC2
Alternative Load to
Coprocessor
Coprocessor
QDSUB
Saturated Subtract with
double
double
CLZ
Count Leading Zeroes