Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The DDR SDR SDRAM Controller (DDRSDRC) is a multiport memory controller. It comprises four slave AHB interfaces.
All simultaneous accesses (four independent AHB ports) are interleaved to maximize memory bandwidth and minimize
transaction latency due to SDRAM protocol.

The DDRSDRC extends the memory capabilities of a chip by providing the interface to an external 16-bit or 32-bit SDR-
SDRAM device and external 16-bit DDR-SDRAM device. The page size supports ranges from 2048 to 16384 and the
number of columns from 256 to 4096. It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. 

The DDRSDRC supports a read or write burst length of 8 locations which frees the command and address bus to
anticipate the next command, thus reducing latency imposed by the SDRAM protocol and improving the SDRAM
bandwidth. Moreover it keeps track of the active row in each bank, thus maximizing SDRAM performance, e.g., the
application may be placed in one bank and data in the other banks. So as to optimize performance, it is advisable to
avoid accessing different rows in the same bank. The DDRSDRC supports a CAS latency of 2 or 3 and optimizes the
read access depending on the frequency.

The features of self-refresh, power-down and deep power-down modes minimize the consumption of the SDRAM device.

The DDRSDRC user interface is compliant with ARM Advanced Peripheral Bus (APB rev2).

Note:

The term “SDRAM device” regroups SDR-SDRAM, Low-power SDR-SDRAM,  Low-power DDR1-SDRAM and 
DDR2-SDRAM devices.