Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

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AMBA compliant interface, interfaces directly to the ARM advanced high performance bus (AHB)

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Four AHB interfaces, management of all accesses maximizes memory bandwidth and minimizes 
transaction latency

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AHB transfer: Word, Half-Word, Byte access

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Supports DDR2-SDRAM, Low-power DDR1-SDRAM, SDR-SDRAM and Low-power SDR-SDRAM

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Numerous configurations supported

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2K, 4K, 8K, 16K row address memory parts 

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SDRAM with  four and eight internal banks

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SDR-SDRAM with 16- or 32-bit data path

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DDR-SDRAM with 16-bit data path

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One Chip Select for SDRAM device (256 Mbyte address space)

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Programming facilities

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Multibank ping-pong access (up to  or 4 banks or 8 banks opened at same time = reduces average latency 
of transactions)

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Timing parameters specified by software

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Automatic refresh operation, refresh rate is programmable

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Automatic update of DS, TCR and PASR parameters (Low-power SDRAM Devices)

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Energy-saving capabilities

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Self-refresh, Power-down, Active Power-down and Deep Power-down modes supported

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SDRAM power-up initialization by software

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CAS Latency of 2, 3 supported

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Reset function supported (DDR2-SDRAM)

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ODT (On-die Termination) not supported

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Auto Precharge command not used

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SDR-SDRAM with 16-bit datapath and eight columns not supported

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DDR2-SDRAM with eight internal banks supported

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Linear and interleaved decoding supported

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SDR-SDRAM or Low-power DDR1-SDRAM with 2 internal banks not supported

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Clock frequency change in Precharge Power-down mode not supported

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OCD (Off-chip Driver) mode not supported