Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

575

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

1.

Wait until the current command execution has successfully terminated.

3.

Check that CMDRDY and NOTBUSY fields are asserted in HSMCI_SR

2.

Program the block length in the card. This value defines the value block_length.

3.

Program the block length in the HSMCI Configuration Register with block_length value.

4.

Configure the fields of the HSMCI_DMA register as follows:



OFFSET field with dma_offset.



CHKSIZE is user defined and set according to DMAC_DCSIZE.



DMAEN is set to true to enable DMA hardware handshaking in the HSMCI. This bit was previously set to 
false.

5.

Issue a WRITE_SINGLE_BLOCK command writing HSMCI_ARG then HSMCI_CMDR.

6.

Program the DMA Controller.

1.

Read the channel register to choose an available (disabled) channel.

2.

Clear any pending interrupts on the channel from the previous DMAC transfer by reading the 
DMAC_EBCISR.

3.

Program the channel registers.

4.

The DMAC_SADDRx register for Channel x must be set to the location of the source data. When the first 
data location is not word aligned, the two LSB bits define the temporary value called dma_offset. The two 
LSB bits of DMAC_SADDRx must be set to 0.

5.

The DMAC_DADDRx register for Channel x must be set with the starting address of the HSMCI_FIFO 
address.

6.

Configure the fields of DMAC_CTRLAx for Channel x as follows:

–DST_WIDTH is set to WORD.

–SRC_WIDTH is set to WORD.

–DCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.

–BTSIZE is programmed with CEILING((block_length + dma_offset) / 4), where the ceiling function is 

the function that returns the smallest integer not less than x.

7.

Configure the fields of DMAC_CTRLBx for Channel x as follows:

–DST_INCR is set to INCR, the block_length value must not be larger than the HSMCI_FIFO 

aperture.

–SRC_INCR is set to INCR.

–FC field is programmed with memory to peripheral flow control mode.

–both DST_DSCR and SRC_DSCR are set to 1 (descriptor fetch is disabled).

–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the DMA controller is 

able to prefetch data and write HSMCI simultaneously.

8.

Configure the fields of DMAC_CFGx for Channel x as follows:

–FIFOCFG defines the watermark of the DMAC channel FIFO.

–DST_H2SEL is set to true to enable hardware handshaking on the destination.

–DST_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host 

Controller.

9.

Enable Channel x, writing one to DMAC_CHER[x]. The DMAC is ready and waiting for request.

7.

Wait for XFRDONE in the HSMCI_SR.