Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
576
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
35.8.6 READ_SINGLE_BLOCK Operation using DMA Controller
35.8.6.1 Block Length is Multiple of 4
1.
Wait until the current command execution has successfully completed.
1.
Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR.
2.
Program the block length in the card. This value defines the value block_length.
3.
Program the block length in the HSMCI Configuration Register with block_length value.
4.
Set RDPROOF bit in HSMCI_MR to avoid overflow.
5.
Configure the fields of the HSMCI_DMA register as follows:
ROPT field is set to 0.
OFFSET field is set to 0.
CHKSIZE is user defined.
DMAEN is set to true to enable DMAC hardware handshaking in the HSMCI. This bit was previously set to
false.
false.
6.
Issue a READ_SINGLE_BLOCK command.
7.
Program the DMA controller.
1.
Read the channel register to choose an available (disabled) channel.
2.
Clear any pending interrupts on the channel from the previous DMA transfer by reading the
DMAC_EBCISR.
DMAC_EBCISR.
3.
Program the channel registers.
4.
The DMAC_SADDRx register for Channel x must be set with the starting address of the HSMCI_FIFO
address.
address.
5.
The DMAC_DADDRx register for Channel x must be word aligned.
6.
Configure the fields of the DMAC_CTRLAx register for Channel x as follows:
–DST_WIDTH is set to WORD.
–SRC_WIDTH is set to WORD.
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with block_length/4.
7.
Configure the fields of the DMAC_CFGx register for Channel x as follows:
–DST_INCR is set to INCR.
–SRC_INCR is set to INCR.
–FC field is programmed with peripheral to memory flow control mode.
–both DST_DSCR and SRC_DSCR are set to 1 (descriptor fetch is disabled).
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the DMA controller is
able to prefetch data and write HSMCI simultaneously.
8.
Configure the fields of the DMAC_CFGx register for Channel x as follows:
–FIFOCFG defines the watermark of the DMA channel FIFO.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host
Controller.
–Enable Channel x, writing one to DMAC_CHER[x]. The DMAC is ready and waiting for request.
8.
Wait for XFRDONE in the HSMCI_SR.