Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

In the previous DMA transfer flow (block length multiple of 4), the DMA controller is configured to use only WORD AHB
access. When the block length is no longer a multiple of 4 this is no longer true. The DMA controller is programmed to
copy exactly the block length number of bytes using 2 transfer descriptors.

1.

Use the previous step until READ_SINGLE_BLOCK then

2.

Program the DMA controller to use a two descriptors linked list.

1.

Read the channel register to choose an available (disabled) channel.

2.

Clear any pending interrupts on the channel from the previous DMA transfer by reading the 
DMAC_EBCISR.

3.

Program the channel registers in the Memory for the first descriptor. This descriptor will be word oriented. 
This descriptor is referred to as LLI_W, standing for LLI word oriented transfer.

4.

The LLI_W.DMAC_SADDRx field in memory must be set with the starting address of the HSMCI_FIFO 
address.

5.

The LLI_W.DMAC_DADDRx field in the memory must be word aligned.

6.

Configure the fields of LLI_W.DMAC_CTRLAx as follows:

–DST_WIDTH is set to WORD.

–SRC_WIDTH is set to WORD.

–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.

–BTSIZE is programmed with block_length/4. If BTSIZE is zero, this descriptor is skipped later.

7.

Configure the fields of LLI_W.DMAC_CTRLBx as follows:

–DST_INCR is set to INCR

–SRC_INCR is set to INCR

–FC field is programmed with peripheral to memory flow control mode.

–SRC_DSCR is set to zero. (descriptor fetch is enabled for the SRC)

–DST_DSCR is set to one. (descriptor fetch is disabled for the DST)

–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, DMA controller is able 

to prefetch data and write HSMCI simultaneously.

8.

Configure the fields of LLI_W.DMAC_CFGx for Channel x as follows:

–FIFOCFG defines the watermark of the DMA channel FIFO.

–DST_REP is set to zero meaning that address are contiguous.

–SRC_H2SEL is set to true to enable hardware handshaking on the destination.

–SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host 

Controller.

9.

Program LLI_W.DMAC_DSCRx with the address of LLI_B descriptor. And set DSCRx_IF to the AHB Layer 
ID. This operation actually links the Word oriented descriptor on the second byte oriented descriptor. When 
block_length[1:0] is equal to 0 (multiple of 4) LLI_W.DMAC_DSCRx points to 0, only LLI_W is relevant.

10. Program the channel registers in the Memory for the second descriptor. This descriptor will be byte oriented. 

This descriptor is referred to as LLI_B, standing for LLI Byte oriented.

11. The LLI_B.DMAC_SADDRx field in memory must be set with the starting address of the HSMCI_FIFO 

address.

12. The LLI_B.DMAC_DADDRx is not relevant if previous word aligned descriptor was enabled. If 1, 2 or 3 

bytes are transferred that address is user defined and not word aligned.

13. Configure the fields of LLI_B.DMAC_CTRLAx as follows:

–DST_WIDTH is set to BYTE.

–SRC_WIDTH is set to BYTE.