Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

Product codes
AT91SAM9N12-EK
Page of 1104
651
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
37.6.4 Clock 
Control
The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See
The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control 
Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform 
Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or 
the stop actions have no effect: only a CLKEN command in the Control Register can re-enable the clock. When the 
clock is enabled, the CLKSTA bit is set in the Status Register.
The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the 
clock. The clock can be stopped by an RB load event in Capture Mode (LDBSTOP = 1 in TC_CMR) or a RC 
compare event in Waveform Mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands have effect 
only if the clock is enabled.
Figure 37-4.  Clock Control
37.6.5  TC Operating Modes
Each channel can independently operate in two different modes:
Capture Mode provides measurement on signals.
Waveform Mode provides wave generation.
The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register. 
In Capture Mode, TIOA and TIOB are configured as inputs.
In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the
external trigger.
37.6.6 Trigger
A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth
external trigger is available to each mode.
Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means
that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is
selected as the clock.
Q
S
R
S
R
Q
CLKSTA
CLKEN
CLKDIS
Stop
Event
Disable
Event
Counter
Clock
Selected
Clock
Trigger