Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The following triggers are common to both modes:



Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR.



SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as 
a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block 
Control) with SYNC set.



Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value 
matches the RC value if CPCTRG is set in TC_CMR.

The channel can also be configured to have an external trigger. In Capture Mode, the external trigger signal can be
selected between TIOA and TIOB. In Waveform Mode, an external event can be programmed on one of the following
signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by setting ENETRG
in TC_CMR.

If an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be
detected.

This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register). 

Capture Mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and
phase on TIOA and TIOB signals which are considered as inputs. 

 shows the configuration of the TC channel when programmed in Capture Mode.

Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value
when a programmable event occurs on the signal TIOA. 

The LDRA parameter in TC_CMR defines the TIOA selected edge for the loading of register A, and the LDRB parameter
defines the TIOA selected edge for the loading of Register B.

RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA.

RB is loaded only if RA has been loaded since the last trigger or the last loading of RB.

Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS) in TC_SR (Status
Register). In this case, the old value is overwritten.

When DMA is used, the RAB register address must be configured as source address of the transfer. The RAB register
provides the next unread value from Register A and Register B. It may be read by the 

DMA 

after a request has been

triggered upon loading Register A or Register B.

The DMAC can only perform access from timer to system memory.

The figure 

 illustrates how the RA and RB registers can be loaded in the

system memory without CPU intervention.