Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
653
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
Figure 37-5. Example of Transfer with DMAC
37.6.10 Trigger Conditions
In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined.
The ABETRG bit in the TC_CMR register selects TIOA or TIOB input signal as an external trigger . The ETRGEDG
parameter defines the edge (rising, falling or both) detected to generate an external trigger. If ETRGEDG = 0 (none), the
external trigger is disabled.
parameter defines the edge (rising, falling or both) detected to generate an external trigger. If ETRGEDG = 0 (none), the
external trigger is disabled.
TIOB
TIOA
RA
RB
Transfer to System Memory
Internal PDC trigger
RA
RB
RA
RB
T1,T2,T3,T4 = System Bus load dependent (Tmin = 8 MCK)
T1
T2
T3
T4
ETRGEDG=1, LDRA=1, LDRB=2, ABETRG=0,
ETRGEDG=3, LDRA=3, LDRB=0, ABETRG=0
TIOB
TIOA
RA
Transfer to System Memory
Internal PDC trigger
RA
RA
T1,T2,T3,T4 = System Bus load dependent (Tmin = 8 MCK)
T1
T2
T3
T4
RA
RA