Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
781
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
Figure 40-36. Example of RTS Drive with Timeguard
40.7.7 SPI
Mode
The Serial Peripheral Interface (SPI) Mode is a synchronous serial data link that provides communication with external
devices in Master or Slave Mode. It also enables communication between processors if an external processor is
connected to the system.
devices in Master or Slave Mode. It also enables communication between processors if an external processor is
connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data
transfer, one SPI system acts as the “master” which controls the data flow, while the other devices act as “slaves'' which
have data shifted into and out by the master. Different CPUs can take turns being masters and one master may
simultaneously shift data into multiple slaves. (Multiple Master Protocol is the opposite of Single Master Protocol, where
one CPU is always the master while all of the others are always slaves.) However, only one slave may drive its output to
write data back to the master at any given time.
transfer, one SPI system acts as the “master” which controls the data flow, while the other devices act as “slaves'' which
have data shifted into and out by the master. Different CPUs can take turns being masters and one master may
simultaneously shift data into multiple slaves. (Multiple Master Protocol is the opposite of Single Master Protocol, where
one CPU is always the master while all of the others are always slaves.) However, only one slave may drive its output to
write data back to the master at any given time.
A slave device is selected when its NSS signal is asserted by the master. The USART in SPI Master mode can address
only one SPI Slave because it can generate only one NSS signal.
only one SPI Slave because it can generate only one NSS signal.
The SPI system consists of two data lines and two control lines:
Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input of the
slave.
slave.
Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master.
Serial Clock (SCK): This control line is driven by the master and regulates the flow of the data bits. The master
may transmit data at a variety of baud rates. The SCK line cycles once for each bit that is transmitted.
may transmit data at a variety of baud rates. The SCK line cycles once for each bit that is transmitted.
Slave Select (NSS): This control line allows the master to select or deselect the slave.
40.7.7.1 Modes of Operation
The USART can operate in SPI Master Mode or in SPI Slave Mode aspresented in
below:.
D0
D1
D2
D3
D4
D5
D6
D7
TXD
Start
Bit
Parity
Bit
Stop
Bit
Baud Rate
Clock
TG = 4
Write
US_THR
TXRDY
TXEMPTY
RTS
Table 40-13. SPI Operating Mode
PIN
USART
SPI Slave
SPI Master
RXD
RXD
MOSI
MISO
TXD
TXD
MISO
MOSI
RTS
RTS
–
CS
CTS
CTS
CS
–