Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
782
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
Operation in SPI Master Mode is programmed by writing 0xE to the USART_MODE field in the Mode Register (US_MR).
In this case the SPI lines must be connected as described below:
In this case the SPI lines must be connected as described below:
The MOSI line is driven by the output pin TXD
The MISO line drives the input pin RXD
The SCK line is driven by the output pin SCK
The NSS line is driven by the output pin RTS
Operation in SPI Slave Mode is programmed by writing to 0xF the USART_MODE field in the Mode Register.
In this case the SPI lines must be connected as described below:
The MOSI line drives the input pin RXD
The MISO line is driven by the output pin TXD
The SCK line drives the input pin SCK
The NSS line drives the input pin CTS
In order to avoid unpredicted behavior, any change of the SPI Mode must be followed by a software reset of the
transmitter and of the receiver (except the initial configuration after a hardware reset). (See
transmitter and of the receiver (except the initial configuration after a hardware reset). (See
40.7.7.2 Baud Rate
In SPI Mode, the baud rate generator operates in the same way as in USART synchronous mode:
However, there are some restrictions:
In SPI Master Mode:
The external clock SCK must not be selected (USCLKS
≠ 0x3), and the bit CLKO must be set to ‘1’ in the US_MR,
in order to generate correctly the serial clock on the SCK pin.
To obtain correct behavior of the receiver and the transmitter, the value programmed in CD must be superior or
equal to 6.
equal to 6.
If the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even to ensure a 50:50
mark/space ratio on the SCK pin, this value can be odd if the internal clock is selected (MCK).
mark/space ratio on the SCK pin, this value can be odd if the internal clock is selected (MCK).
In SPI Slave Mode:
The external clock (SCK) selection is forced regardless of the value of the USCLKS field in the US_MR. Likewise,
the value written in US_BRGR has no effect, because the clock is provided directly by the signal on the USART
SCK pin.
the value written in US_BRGR has no effect, because the clock is provided directly by the signal on the USART
SCK pin.
To obtain correct behavior of the receiver and the transmitter, the external clock (SCK) frequency must be at least
6 times lower than the system clock.
6 times lower than the system clock.
40.7.7.3 Data Transfer
Up to nine data bits are successively shifted out on the TXD pin at each rising or falling edge (depending of CPOL and
CPHA) of the programmed serial clock. There is no Start bit, no Parity bit and no Stop bit.
CPHA) of the programmed serial clock. There is no Start bit, no Parity bit and no Stop bit.
The number of data bits is selected by the CHRL field and the MODE 9 bit in the US_MR. The nine bits are selected by
setting the MODE 9 bit regardless of the CHRL field. The MSB data bit is always sent first in SPI Mode (Master or Slave).
setting the MODE 9 bit regardless of the CHRL field. The MSB data bit is always sent first in SPI Mode (Master or Slave).
Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL
bit in the US_MR. The clock phase is programmed with the CPHA bit. These two parameters determine the edges of the
clock signal upon which data is driven and sampled. Each of the two parameters has two possible states, resulting in four
possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter
bit in the US_MR. The clock phase is programmed with the CPHA bit. These two parameters determine the edges of the
clock signal upon which data is driven and sampled. Each of the two parameters has two possible states, resulting in four
possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter