Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
957
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
44.6
Functional Description
The LCD module integrates the following digital blocks:
DMA Engine Address Generation (DEAG). This block performs data prefetch and requests access to the AHB
interface.
interface.
Input FIFO, stores the stream of pixels.
Color Lookup Table (CLUT). These 256 RAM-based lookup table entries are selected when the color depth is set
to 1, 2, 4 or 8 bpp.
to 1, 2, 4 or 8 bpp.
Output FIFO, stores the pixel prior to display.
LCD Timing Engine, provides a fully programmable HSYNC-VSYNC interface.
The DMA controller reads the image through the AHB master interface. The LCD controller engine formats the display
data and writes the final pixel into the output FIFO. The programmable timing engine drives a valid pixel onto the
LCD_DAT[23:0] display bus.
data and writes the final pixel into the output FIFO. The programmable timing engine drives a valid pixel onto the
LCD_DAT[23:0] display bus.
44.6.1 Timing Engine Configuration
44.6.1.1 Pixel Clock Period Configuration
The pixel clock (PCLK) generated by the timing engine is the source clock (SCLK) divided by the field CLKDIV in the
LCDC_LCDCFG0 register. The source clock can be selected between the system clock and the 2x system clock with the
field CLKSEL located in the LCDC_LCDCFG0 register. The Pixel Clock period formula is given below:
LCDC_LCDCFG0 register. The source clock can be selected between the system clock and the 2x system clock with the
field CLKSEL located in the LCDC_LCDCFG0 register. The Pixel Clock period formula is given below:
The Pixel Clock polarity is also programmable.
44.6.1.2 Horizontal and Vertical Synchronization Configuration
The following fields are used to configure the timing engine:
HSPW field
VSPW field
VFPW field
VBPW field
HFPW field
HBPW field
PPL field
RPF field
The polarity of output signals is also programmable.
44.6.1.3 Timing Engine Power Up Software Operation
The following sequence is used to enable the display:
1.
Configure LCD timing parameters, signal polarity and clock period.
2.
Enable the Pixel Clock by writing one to the CLKEN field of the LCDC_LCDEN register.
3.
Poll CLKSTS field of the LCDC_LCDSR register to check that the clock is running.
4.
Enable Horizontal and Vertical Synchronization by writing one to the SYNCEN field of the LCDC_LCDEN register.
5.
Poll LCDSTS field of the LCDC_LCDSR register to check that the synchronization is up.
6.
Enable the display power signal writing one to the DISPEN field of the LCDC_LCDEN register.
7.
Poll DISPSTS field of the LCDC_LCDSR register to check that the power signal is activated.
The GUARDTIME field of the LCDC_LCDCFG5 register is used to configure the number of frames before the assertion
of the DISP signal.
of the DISP signal.
PCLK
SCLK
CLKDIV
2
+
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