Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
959
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
44.6.2.5 DMA Interrupt Generation
The DMA controller operation sets the following interrupt flags in the interrupt status register CHXISR:
DMA field indicates that the DMA transfer is completed.
DSCR field indicates that the descriptor structure is loaded in the DMA controller.
ADD field indicates that a descriptor has been added to the descriptor queue.
DONE field indicates that the channel transfer has terminated and the channel is automatically disabled.
44.6.2.6 DMA Address Alignment Requirements
When programming the DSCR.CHXADDR field of the DSCR structure the following requirement must be met.
44.6.3 Display
Software Configuration
44.6.3.1 System Bus Access Attributes
These attributes are defined to improve bandwidth of the pixel stream.
DLBO field: when set to one only defined burst lengths are performed when the DMA channel retrieves the data
from the memory.
from the memory.
BLEN field: defines the maximum burst length of the DMA channel.
Table 44-5. DMA address alignment when CLUT Mode is selected
CLUT Mode
DMA address alignment
1 bpp
8 bit
2 bpp
8 bit
4 bpp
8 bit
8 bpp
8 bit
Table 44-6. DMA address alignment when RGB Mode is selected
RGB Mode
DMA address alignment
12 bpp RGB 444
16 bit
16 bpp ARGB 4444
16 bit
16 bpp RGBA 4444
16 bit
16 bpp RGB 565
16 bit
16 bpp TRGB 1555
16 bit
18 bpp RGB 666
32 bit
18 bpp RGB 666 PACKED
8 bit
19 bpp TRGB 1666
32 bit
19 bpp TRGB 1666
8 bit
24 bpp RGB 888
32 bit
24 bpp RGB 888 PACKED
8 bit
25 bpp TRGB 1888
32 bit
32 bpp ARGB 8888
32 bit
32 bpp RGBA 8888
32 bit