Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
958
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
44.6.1.4 Timing Engine Power Down Software Operation
The following sequence is used to disable the display:
1.
Disable the DISP signal writing DISPDIS field of the LCDC_LCDDIS register.
2.
Poll DISPSTS field of the LCDC_LCDSR register to verify that the DISP is no longer activated.
3.
Disable the hsync and vsync signals by writing one to SYNCDIS field of the LCDC_LCDDIS register.
4.
Poll LCDSTS field of the LCDC_LCDSR register to check that the synchronization is off.
5.
Disable the Pixel clock by writing one in the CLKDIS field of the LCDC_LCDDIS register.
44.6.2 DMA
Software Operations
44.6.2.1 DMA Channel Descriptor (DSCR) Alignment and Structure
The DMA Channel Descriptor (DSCR) must be word aligned.
The DMA Channel Descriptor structure contains three fields:
DSCR.CHXADDR: Frame Buffer base address register
DSCR.CHXCTRL: Transfer Control register
DSCR.CHXNEXT: Next Descriptor Address register
44.6.2.2 Programming a DMA Channel
1.
Check the status of the channel reading the CHXCHSR register.
2.
Write the channel descriptor (DSCR) structure in the system memory by writing DSCR.CHXADDR Frame base
address, DSCR.CHXCTRL channel control and DSCR.CHXNEXT next descriptor location.
address, DSCR.CHXCTRL channel control and DSCR.CHXNEXT next descriptor location.
3.
If more than one descriptor is expected, the DFETCH field of DSCR.CHXCTRL is set to one to enable the descrip-
tor fetch operation.
tor fetch operation.
4.
Write the DSCR.CHXNEXT register with the address location of the descriptor structure and set DFETCH field of
the DSCR.CHXCTRL register to one.
the DSCR.CHXCTRL register to one.
5.
Enable the relevant channel by writing one to the CHEN field of the CHXCHER register.
6.
An interrupt may be raised if unmasked when the descriptor has been loaded.
44.6.2.3 Disabling a DMA channel
1.
Clear the DFETCH bit in the DSCR.CHXCTRL field of the DSCR structure will disable the channel at the end of the
frame.
frame.
2.
Set the DSCR.CHXNEXT field of the DSCR structure will disable the channel at the end of the frame.
3.
Writing one to the CHDIS field of the CHXCHDR register will disable the channel at the end of the frame.
4.
Writing one to the CHRST field of the CHXCHDR register will disable the channel immediately. This may occur in
the middle of the image.
the middle of the image.
5.
Poll CHSR field in the CHXCHSR register until the channel is successfully disabled.
44.6.2.4 DMA Dynamic Linking of a New Transfer Descriptor
1.
Write the new descriptor structure in the system memory.
2.
Write the address of the new structure in the CHXHEAD register.
3.
Add the new structure to the queue of descriptors by writing one to the A2QEN field of the CHXCHER register.
4.
The new descriptor will be added to the queue on the next frame.
5.
An interrupt will be raised if unmasked, when the head descriptor structure has been loaded by the DMA channel.
Table 44-4. DMA Channel Descriptor Structure
System Memory
Structure Field for channel CHX
DSCR + 0x0
ADDR
DSCR + 0x4
CTRL
DSCR + 0x8
NEXT