Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
999
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
42.7.11
PWM Channel Period Register
Name:
PWM_CPRD[0..3]
Addresses:
0xFFFB8208 [0], 0xFFFB8228 [1], 0xFFFB8248 [2], 0xFFFB8268 [3]
Access:
Read/Write
Only the first 16 bits (internal channel counter size) are significant.
• CPRD: Channel Period
If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
calculated:
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
256, 512, or 1024). The resulting period formula will be:
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
or
If the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
calculated:
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
256, 512, or 1024). The resulting period formula will be:
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
or
31
30
29
28
27
26
25
24
CPRD
23
22
21
20
19
18
17
16
CPRD
15
14
13
12
11
10
9
8
CPRD
7
6
5
4
3
2
1
0
CPRD
X
CPRD
×
(
)
MCK
--------------------------------
CRPD
DIVA
×
(
)
MCK
------------------------------------------
CRPD
DIVAB
×
(
)
MCK
----------------------------------------------
2
X
CPRD
×
×
(
)
MCK
------------------------------------------
2
CPRD
DIVA
×
×
(
)
MCK
----------------------------------------------------
2
CPRD
×
DIVB
×
(
)
MCK
----------------------------------------------------