Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Power Up and Reset Sequence
Intel
®
Atom™ Processor E3800 Product Family
102
Datasheet
7.3
Power Down Sequences
7.3.1
S0 to S3 and S4/S5/G3 Sequence
Entry to Sleep states (S3,S4, S5) is initiated by any of the following methods:
•
Setting the desired sleep type in PM1_CNT.SLP_TYP and setting PM1_CNT.SLP_EN.
•
Detection of an external catastrophic temperature event may cause a transition to
S5, if the system is designed to do so.
S5, if the system is designed to do so.
The following sequence applies to S0-S3 and S0-S4/S5 transitions.
1. The Operating System Power Management (OSPM) will handle the enabling or
disabling of interrupt generation after S3 resume. The Operating System Power
Management (OSPM) will need to read and clear Wake status information and the
processing of the clearing wake status which will include enabling interrupts (both
at the core level and platform level).
Management (OSPM) will need to read and clear Wake status information and the
processing of the clearing wake status which will include enabling interrupts (both
at the core level and platform level).
2. All interrupts in the processor need to be disabled before the S3 sequence is
started (and re-enabled on exit). The CPU APIC must be disabled.
3. When the desired sleep state is set in the PM1_CNT.TYP and PM1_CNT.SLP_EN
registers, a sleep state request is sent to the PMC.
4. The PMC flushes all the internal buffers to main memory.
5. The PMC places the PCI Express* devices into the L2/L3 state. The PMC will wait
until the PCI Express* devices are in the L2/L3 state before preceding. A timeout
will occur in 1 ms if there is a non-functional PCI Express* device.
will occur in 1 ms if there is a non-functional PCI Express* device.
Additional assumptions:
•
Entry to a Cx state is mutually exclusive with software-initiated entry to a Sleep
state. This is because the processor(s) can only perform one register access at a
time. This requirement is enforced by the CPU as well as the OS. The system may
hang if it attempts to do a C-state and S-state at the same time.
state. This is because the processor(s) can only perform one register access at a
time. This requirement is enforced by the CPU as well as the OS. The system may
hang if it attempts to do a C-state and S-state at the same time.
•
The G3 system state cannot be entered via any software mechanism. The G3 state
indicates a complete loss of power. In this state, the RTC well may or may not be
powered by an external coin cell battery.
indicates a complete loss of power. In this state, the RTC well may or may not be
powered by an external coin cell battery.
•
An external Power Management Controller (PMIC/EC) can be used to put the SoC in
G3 when the S4/S5 state is requested by the SoC. This is done to save power in
S4/S5 state. This G3 like state, known as SoC G3, is enabled by removing SUS rails
via when the SUSPWRDNACK pin is asserted on power down. Doing so prevents the
use of any of SUS wake events including USB, RTC, and GPIOs including the power
button. The external Power Management Controller (or re-application of power) is
required to return to S0.
G3 when the S4/S5 state is requested by the SoC. This is done to save power in
S4/S5 state. This G3 like state, known as SoC G3, is enabled by removing SUS rails
via when the SUSPWRDNACK pin is asserted on power down. Doing so prevents the
use of any of SUS wake events including USB, RTC, and GPIOs including the power
button. The external Power Management Controller (or re-application of power) is
required to return to S0.