Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1062
Datasheet
15.7.20
iunit_MISR1_type (MISR1)—Offset C4h
OCP Master Read Data
Access Method
Default: FFFFFFFFh
15.7.21
iunit_MISR2_type (MISR2)—Offset C8h
OCP Master Address and Control
Access Method
Default: FFFFFFFFh
31
28
24
20
16
12
8
4
0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
MISR0
Bit
Range
Default &
Access
Description
31:0
FFFFFFFFh
RW/C
MISR0:
MISR0: Write to this register address clears this MISR. This is a 8:1
compression MISR capturing the 256-bit write data on the OCP interface between
ISP_CSS and Iunit wrapper.
Type:
PCI Configuration Register
(Size: 32 bits)
MISR1:
31
28
24
20
16
12
8
4
0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
MI
S
R
1
Bit
Range
Default &
Access
Description
31:0
FFFFFFFFh
RW/C
MISR1:
MISR1: Write to this register address clears this MISR. This is a 8:1
compression MISR capturing the 256-bit read return data on the OCP interface between
ISP_CSS and Iunit wrapper.
Type:
PCI Configuration Register
(Size: 32 bits)
MISR2:
31
28
24
20
16
12
8
4
0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
MI
SR2
Bit
Range
Default &
Access
Description
31:0
FFFFFFFFh
RW/C
MISR2:
MISR2: Write to this register address clears this MISR. This is a 4:1
compression MISR capturing the control signals on the OCP Master port in the Iunit.