Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1072
Datasheet
15.7.33
iunit_IUNIT_STATUS_type (IUNIT_STATUS)—Offset F8h
IUNIT Status Register
Access Method
Default: 0000EB01h
18:16
0h
RW
CSI_HS_CALIB_LOOP_DELAY:
CSI_HS_CALIB_LOOP_DELAY: Delay after applying a
new RCOMP value to the AFE, before sampling the count up/down input from the AFE.
0h=)50-53ns; 1h=)60ns; 2h=)70-72ns; 3h=)80-83ns; 4h=)90ns; 5h=)100-102ns;
6h=)125-128ns; 7h=)150ns. At the start of each RCOMP calibration cycle, the state
machine waits for 8x this delay before starting to sample the count up/down signal.
15:11
0h
RW
RSVD_15_11:
Reserved
10
0b
RW
CSI3_HS_RCOMP_OVR_ENABLE:
CSI3_HS_RCOMP_OVR_ENABLE: If set, then the
CSI_HS_RCOMP_OVRD field is used as the RCOMP value during the update cycle for CSI
port 3. If clear, then the output of the RCOMP calibration engine (stored in
CSI_RCOMP_CALIBRATION_VALUE field of IUNIT_RCOMP_STATUS register) is used as
the RCOMP value during the update cycle for CSI port 3.
9
0b
RW
CSI2_HS_RCOMP_OVR_ENABLE:
CSI2_HS_RCOMP_OVR_ENABLE: If set, then the
CSI_HS_RCOMP_OVRD field is used as the RCOMP value during the update cycle for CSI
port 2. If clear, then the output of the RCOMP calibration engine (stored in
CSI_RCOMP_CALIBRATION_VALUE field of IUNIT_RCOMP_STATUS register) is used as
the RCOMP value during the update cycle for CSI port 2.
8
0b
RW
CSI1_HS_RCOMP_OVR_ENABLE:
CSI1_HS_RCOMP_OVR_ENABLE: If set, then the
CSI_HS_RCOMP_OVRD field is used as the RCOMP value during the update cycle for CSI
port 1. If clear, then the output of the RCOMP calibration engine (stored in
CSI_RCOMP_CALIBRATION_VALUE field of IUNIT_RCOMP_STATUS register) is used as
the RCOMP value during the update cycle for CSI port 1.
7:1
0h
RW
CSI_HS_RCOMP_OVR_CODE:
CSI_HS_RCOMP_OVR_CODE: Software defined value
to use as the RCOMP value for CSI[1-3] ports if the CSI[1-3]_HS_RCOMP_OVR_ENABLE
fields are set.
0
1b
RW
CSI_HS_RCOMP_ENABLE:
CSI_HS_RCOMP_ENABLE: Enable CSI HS RCOMP. (Note:
This bit does not affect the initial RCOMP at the de-assertion of reset which is controlled
by the fuse FB_disable_initial_RCOMP.)
Bit
Range
Default &
Access
Description
Type:
PCI Configuration Register
(Size: 32 bits)
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 0 0 0 0 0 0 1
RSVD_31_18
IS
CLK
CZCLK
RSVD_7_7
TC
G
S
M
RSVD_3_3
LCG
S
M
ISP_BUSY
Bit
Range
Default &
Access
Description
31:18
0h
RO
RSVD_31_18:
Reserved
17:13
07h
RO
ISCLK:
Reflects the value of cck_isp_isclk_ratio_zcznfwh input pin.
12:8
0Bh
RO
CZCLK:
Reflects the value of cck_xxx_czclk_ratio_zcznfwh input pin.