Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1152
Datasheet
Default: 00000000h
15.8.45
reg_gpd_irq_ctrl_reg_irq_level_not_pulse_type
(gpd_irq_ctrl_reg_irq_level_not_pulse)—Offset 514h
Access Method
Default: 00000000h
15.8.46
reg_gpd_irq_ctrl_reg_irq_str_out_enable_type
(gpd_irq_ctrl_reg_irq_str_out_enable)—Offset 518h
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
reg_irq_e
n
able
Bit
Range
Default &
Access
Description
31:0
0h
RW
reg_irq_enable:
Indicates for each bit whether an interrupt cause as monitored by the
req_irq_status register also affects the IRQ pin (value='1') or not (value='0')
Type:
Memory Mapped I/O Register
(Size: 32 bits)
gpd_irq_ctrl_reg_irq_level_not_pulse:
ISPMMADR Type:
PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference:
[B:0, D:3, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
reg
_
irq_le
ve
l_not_p
ulse
Bit
Range
Default &
Access
Description
31:0
0h
RW
reg_irq_level_not_pulse:
Indicates for each bit whether an interrupt cause is
translated into a pulse (value='0') or into a constant level '1' (value='1') on the IRQ pin
Type:
Memory Mapped I/O Register
(Size: 32 bits)
gpd_irq_ctrl_reg_irq_str_out_enable:
ISPMMADR Type:
PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference:
[B:0, D:3, F:0] + 10h