Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Electrical Specifications
Intel
®
Atom™ Processor E3800 Product Family
158
Datasheet
9.
Informative. Transmitter jitter must be measured at source connector pins using a signal analyzer that has a 2nd order
PLL with tracking bandwidth of 20MHz (for D10.2 pattern) and damping factor of 1.428.
10.
Measured at 1.62 GHz and 2.7 GHz (if supported), within the frequency tolerance range. Time-domain measurement using
a spectrum analyzer.
11.
All DisplayPort Main Link lanes as well as AUX CH must be AC coupled. AC coupling capacitors must be placed on the
transmitter side. Placement of AC coupling capacitors on the receiver side is optional.
12.
0.20* Tcharacter @165MHz
NOTES:
1.
Results in the bit rate of 1Mbps including the overhead of ManchesterII coding.
2.
Period after the AUX CH STOP condition for which the bus is parked
3.
Equal to 48 ns maximum. The transmitting Device is a Source Device for a Request transaction and a
Sink Device for a Reply Transaction
4.
Equal to 24 ns maximum. The transmitting Device is a Source Device for a Request transaction and a
Sink Device for a Reply Transaction.
5.
Total drive current of the transmitter when it is shorted to its ground.
6.
The AUX CH AC-coupling capacitor placed on both the DP upstream and downstream devices.
9.6.6.2
Analog VGA Display AC Specification
The VGA DAC (digital-to-analog converter) consists of three identical 8-bit DACs to
provide red, green, and blue color components. Each DAC can output a current from 0
to 255 units of current, where one unit of current (LSB) is defined based on the VESA
video signal standard.
provide red, green, and blue color components. Each DAC can output a current from 0
to 255 units of current, where one unit of current (LSB) is defined based on the VESA
video signal standard.
Table 112. DDI AUX Channel AC Specification
Symbol
Parameter
Min
Typ
Max
Units
Notes
1
UI
AUX Unit Interval
0.4
0.5
0.6
µs
1
T
AUX-BUS-PARK
AUX CH bus park time
10
ns
2
T
CYCLE-to-CYCLE
Jitter
Maximum allowable UI variation within a
single transaction at connector pins of a
transmitting Device
single transaction at connector pins of a
transmitting Device
0.08
UI
3
Maximum allowable variation for adjacent
bit times within a single transaction at
connector pins of a transmitting Device
bit times within a single transaction at
connector pins of a transmitting Device
0.04
UI
4
I
AUX_SHORT
AUX Short Circuit Current Limit
90
mA
5
C
AUX
AC Coupling Capacitor
75
200
nF
6
Table 113. R,G,B / VGA DAC Display AC Specification (Sheet 1 of 2)
Symbol
Parameter
Min
Nom
Max
Unit
Notes
Pixel Clock Frequency = 300 MHz
T
RISE
R,G,B Video Rise
TIme
TIme
0.33
1.67
ns
1,2,8 (10-90% of “black”-to-
”white” video transition)
”white” video transition)
T
FALL
R,G,B Video Fall
TIme
TIme
0.33
1.67
ns
1,3,8 (90-10% of “black”-to-
”white” video transition)
”white” video transition)
T
SETTLING
Settling time
1.0
ns
1,4,8
VO
Video Channel-to-
Channel output
skew
Channel output
skew
0.833
ns
1,5,8
Overshoot/
Undershoot
Undershoot
-0.084
+0.084
V
1,6,8 (0.7V full-scale voltage step)