Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1849
16.8.25
Error Interrupt Signal Enable Register (ERR_INT_SIG_EN)—
Offset 3Ah
This register is used to select which interrupt status is sent to the Host System as the
interrupt. These status bits all share the same 1 bit interrupt line. Setting any of these
bits to 1 enables interrupt generation.
Access Method
Default: 0000h
8
0b
RW
Card Interrupt Signal Enable (crd_int_sig_en):
•
•
1 = enabled
•
0 = masked
7
0b
RW
Card Removal Signal Enable (crd_rm_sig_en):
•
•
1 = enabled
•
0 = masked
6
0b
RW
Card Insertion Signal Enable (crd_ins_sig_en):
•
•
1 = enabled
•
0 = masked
5
0b
RW
Buffer Read Ready Signal Enable (buf_rd_rdy_sig_en):
•
•
1 = enabled
•
0 = masked
4
0b
RW
Buffer Write Ready Signal Enable (buf_wr_rdy_sig_en):
•
•
1 = enabled
•
0 = masked
3
0b
RW
DMA Interrupt Signal Enable (dma_int_sig_en):
•
•
1 = enabled
•
0 = masked
2
0b
RW
Block Gap Event Signal Enable (blk_gap_event_sig_en):
•
•
1 = enabled
•
0 = masked
1
0b
RW
Transfer Complete Signal Enable (tx_comp_sig_en):
•
•
1 = enabled
•
0 = masked
0
0b
RW
Command Complete Signal Enable (cmd_comp_sig_en):
•
•
1 = enabled
•
0 = masked
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 16 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:18, F:0] + 10h