Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
1932
Datasheet
17.5.13
Secondary Control Block Base Address (SCTLBA)—Offset 1Ch
This 4-byte I/O space is used in Native Mode for the Secondary Controller's Control 
Block.
Access Method
Default: 00000001h
17.5.14
Legacy IDE Base Address / AHCI Index Data Pair Base Address 
(LBAR)—Offset 20h
This BAR is used to allocate I/O space for the SFF-8038i mode of operation (aka Bus 
Master IDE) and if CC.SCC is not 01h, it is used to allocate I/O space for the AHCI 
index/data pair mechanism as well. Note that hardware does not clear the BA bits 
(including BA4) when switching from IDE mode to non-IDE mode or vice versa. BIOS is 
responsible for clearing those bits to 0 since the number of writable bits changes after 
mode switching.
Access Method
Default: 00000001h
Type: 
PCI Configuration Register
(Size: 32 bits)
SCTLBA: 
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
RS
VD0
BAR
RS
VD1
RT
E
Bit 
Range
Default & 
Access
Description
31:16
0b
RO
RSVD0: 
Reserved
15:2
0h
RW
Base Address (BAR): 
Base address of the I/O space (4 consecutive I/O locations).
1
0b
RO
RSVD1: 
Reserved
0
1h
RO
Resource Type Indicator (RTE): 
Indicates a request for IO space.
Type: 
PCI Configuration Register
(Size: 32 bits)
LBAR: 
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
RS
VD0
BA
RS
VD1
RT
E
Bit 
Range
Default & 
Access
Description
31:16
0b
RO
RSVD0: 
Reserved