Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

1934

Datasheet

This register is initialized to logic 0 by the assertion of Backbone Reset. This register 

can be written only once after Backbone Reset de-assertion.

Default: 00000000h

Default: 80h

Default: 0100h

PCI Configuration Register

(Size: 32 bits)

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SS

ID

SSV

ID

31:16

0000h

RW/O

This is written by BIOS. No hardware action taken on this 

value.

15:0

0000h

RW/O

This is written by BIOS. No hardware action taken on 

this value.

PCI Configuration Register

(Size: 8 bits)

7

4

0

1

0

0

0

0

0

0

0

CP

7:0

80h

RW/L

Indicates that the first capability pointer offset is offset 80h 

(the Message Signaled Interrupt capability). The following capability structures are 

linked by default which is meant for non-IDE mode: CAP.CP - 80h (MSI) - 70h (PCI 

Power) - A8h (SATA) - 00h end. BIOS may alter the capability structure list above (by 

programming a leading capability structure's Next Pointer field) if BIOS wants to bypass 

any specific capability.[Br] If BIOS intends to operate in IDE mode, BIOS is requested to 

program this field to 70h and the subsequent capability list as such: CAP.CP - 70h (PCI 

Power) - end. The RW/L register attribute allows for flexibility in determining the 

capability structure available in this PCI function. Refer to SATAGC.REGLOCK description 

in order to lock the register to become RO.

PCI Configuration Register

(Size: 16 bits)