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Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
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Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
1939
17.5.26
IDE I/O Configuration (IIOC)—Offset 54h
This register is not used by SATA controller.
Access Method
Default: 00000000h
17.5.27
PCI Power Management Capability ID (PID)—Offset 70h
Access Method
Default: A801h
17.5.28
PCI Power Management Capabilities (PC)—Offset 72h
Access Method
Bit 
Range
Default & 
Access
Description
15:0
0h
RW
RSVD: 
Reserved
Type: 
PCI Configuration Register
(Size: 32 bits)
IIOC: 
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
Bit 
Range
Default & 
Access
Description
31:0
0h
RW
RSVD: 
Reserved
Type: 
PCI Configuration Register
(Size: 16 bits)
PID: 
15
12
8
4
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
NEXT
CID
Bit 
Range
Default & 
Access
Description
15:8
A8h
RW/L
Next Capability (NEXT): 
A8h is location of the Serial ATA Capability structure. This is 
recommended for non-IDE mode. If the controller is to operate in IDE mode, BIOS is 
requested to program this field to 00h indicating the end (recommended setting). The 
RW/L register attribute allows for flexibility in determining the capability structure 
available in this PCI function. Refer to SATAGC.REGLOCK description in order to lock the 
register to become RO.
7:0
01h
RO
Cap ID (CID): 
Indicates that this pointer is a PCI power management capability.
Type: 
PCI Configuration Register
(Size: 16 bits)
PC: