Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

1944

Datasheet

By default, the SATA ports are set (by hardware) to the disabled state (e.g. bits[5:0] 

== 0) as a result of an initial power on reset. When enabled by software, the ports can 

transition between the on, partial, and slumber states and can detect devices. When 

disabled, the port is in the off state and cannot detect any devices. Note: AHCI specific 

notes: If an AHCI-aware or RAID enabled operating system is being booted then 

system BIOS shall insure that all supported SATA ports are enabled prior to passing 

control to the OS. Once the AHCI aware OS is booted it becomes the enabling/disabling 

policy owner for the individual SATA ports. This is accomplished by manipulating a 

port's PxSCTL.DET and PxCMD.SUD fields. Because an AHCI or RAID aware OS will 

typically not have knowledge of the PxE bits and because the PxE bits act as master on/

off switches for the ports, pre-boot software must insure that these bits are set to 1 

prior to booting the OS, regardless as to whether or not a device is currently on the 

port.

Default: 0000h

5

1h

RW

This bit changes number of SATA port 

availability within each SATA controller. When MAP.SPD[5] is 1 and MAP.SPD[4] is 1, this 

bit is reserved and is read-only 1 else it's RW-zero. When this bit is 0: Up to 2 SATA 

ports are available in the SATA controller 1 with port[1:0]. When this bit to 1: Up to 2 

SATA ports are available in the SATA controller 1 with port [1:0]. For SMS=IDE mode, 

this bit should be 0 (note that this irrespective of the number of SATA ports). The 

number of port availability in this controller shall be discoverable thru this controller's 

config PCS.PxE, AHCI CAP.NP and AHCI PI[x] register fields. Prior to changing the state 

of this bit, all ports must be in quiescent state with no commands outstanding. Refer to 

Single and Dual Controller Switching Requirement for additional software and hardware 

requirements.

4:2

0b

RO

Reserved

1:0

0h

RO

This register is reserved.

PCI Configuration Register

(Size: 16 bits)

15

12

8

4

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

OR

M

RSVD

0

RSVD

P1P

P0P

RSVD

1

P1E

P0E

15

0h

RW

When cleared, the SATA controller will not retry after an OOB 

failure. When set, the SATA controller will continue to retry after an OOB failure until 

successful (infinite retry). BIOS is requested to program this field to 1.

14

0b

RO

Reserved

13:10

0h

RO

Reserved

9

0h

RO

Same as P0P, except for port 1.