Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

1964

Datasheet

This register controls various global actions of the HBA.

Default: 00000000h

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:19, F:0] + 24h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AE

RSVD

0

MR

S

M

IE

HR

31

0h

RW

When set, indicates that an AHCI driver is loaded and 

communication to the HBA shall be via AHCI mechanisms. This can be used by an HBA 

that supports both legacy mechanisms (such as SFF-8038i) and AHCI to know when the 

HBA is running under an AHCI driver. When set, software shall only talk to the HBA 

using AHCI. The HBA will not have to allow command processing via both AHCI and 

legacy mechanisms. When cleared, software will only communicate with the HBA using 

legacy mechanisms. Software shall set this bit to 1 before accessing other AHCI 

registers. Note: The implementation of this bit is dependent upon the value of the 

CAP.SAM bit. If CAP.SAM is 0, then GHC.AE should be RW and shall have a reset value of 

0. If CAP.SAM is 1, then AE shall be read only and shall have a reset value of 1.

30:3

0b

RO

Reserved

2

0h

RO

When set to 1 by hardware, indicates that 

the HBA requested more than one MSI vector but has reverted to using the first vector 

only. When this bit is cleared to 0, the HBA has not reverted to single MSI mode (i.e. 

hardware is already in single MSI mode, software has allocated the number of messages 

requested, or hardware is sharing interrupt vectors if MC.MME ( MC.MMC). The HBA may 

revert to single MSI mode when the number of vectors allocated by the host is less than 

the number requested. This bit shall only be set to 1 when the following conditions hold: 

MC.MSIE = 1 (MSI is enabled); MC.MMC ) 0 (multiple messages requested); MC.MME ) 

0 (more than one message allocated); MC.MME != MC.MMC (messages allocated not 

equal to number requested). When this bit is set to 1, single MSI mode operation is in 

use and software is responsible for clearing bits in the IS register to clear interrupts. 

This bit shall be cleared to 0 by hardware when any of the four conditions stated is false. 

This bit is also cleared to 0 when MC.MSIE = 1 and MC.MME = 0h. In this case, the 

hardware has been programmed to use single MSI mode, and is not reverting to that 

mode. The HBA shall always revert to single MSI mode when the number of vectors 

allocated by the host is leass than the number requested. Value of MRSM is a don't care 

when GHC.HR=1.

1

0h

RW

This global bit enables interrupts from the HBA. When cleared 

(reset default), all interrupt sources from all ports are disabled. When set, interrupts are 

enabled.

0

0h

RW/1S

When set by SW, this bit causes an internal reset of the HBA. All 

state machines that relate to data transfers and native command queuing will return to 

an idle condition, and all ports will be re-initialized via COMRESET. When the HBA has 

performed the reset action, it will reset this bit to 0. A software write of 0 will have no 

effect. For a description on which bits are reset when this bit is set, see the AHCI 

specification, section 10.3.3.