Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1965
17.8.3
Interrupt Status (IS)—Offset 8h
This register indicates which of the ports within the controller have an interrupt pending
and require service.
Access Method
Default: 00000000h
17.8.4
Ports Implemented (GHC_PI)—Offset Ch
This register indicates which ports are exposed to the HBA. It is loaded by platform
BIOS. It indicates which ports that the device supports are available for software to
use. Any available port may not be implemented. There is BIOS programming
requirement on the PI register. Please refer to section 7.9.13.1.1 for details.
Access Method
Default: 00000000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
IS:
ABAR Type:
PCI Configuration Register (Size: 32 bits)
ABAR Reference:
[B:0, D:19, F:0] + 24h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RS
VD0
IPS1
IPS0
Bit
Range
Default &
Access
Description
31:2
0b
RO
RSVD0:
Reserved
1
0h
RW/1C
Interrupt Pending Status Port 1 (IPS1):
If set, indicates that port 1 has an interrupt
pending. Software can use this information to determine which ports require service
after an interrupt. This bit is only applicable to project(s): That has port 1 physically.
0
0h
RW/1C
Interrupt Pending Status Port 0 (IPS0):
If set, indicates that port 0 has an interrupt
pending. Software can use this information to determine which ports require service
after an interrupt. This bit is only applicable to project(s): That has port 0 physically.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
GHC_PI:
ABAR Type:
PCI Configuration Register (Size: 32 bits)
ABAR Reference:
[B:0, D:19, F:0] + 24h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSV
D
0
PI1
PI0
Bit
Range
Default &
Access
Description
31:2
0b
RO
RSVD0:
Reserved