Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

1982

Datasheet

Default: 00000000h

Default: 00000000h

15:0

0000h

RW/1C

The ERR field contains error information for use by host software in 

determining the appropriate response to the error condition. If one or more of bits 11:8 

of this register are set, the controller will stop the current transfer. 15:12 Reserved 11 

Internal Error (E): The SATA controller failed due to a master or target abort when 

attempting to access system memory. 10 Protocol Error (P): A violation of the Serial ATA 

protocol was detected. 9 Persistent Communication or Data Integrity Error (C): A 

communication error that was not recovered occurred that is expected to be persistent. 

Persistent communications errors may arise from faulty interconnect with the device, 

from a device that has been removed or has failed, or a number of other causes. 8 

Transient Data Integrity Error (T): A data integrity error occurred that was not 

recovered by the interface. 7:2 Reserved 1 Recovered Communications Error (M): 

Communications between the device and host was temporarily lost but was re-

established. This can arise from a device temporarily being removed, from a temporary 

loss of Phy synchronization, or from other causes and may be derived from the PhyNRdy 

signal between the Phy and Link layers. 0 Recovered Data Integrity Error (I): A data 

integrity error occurred that was recovered by the interface through a retry operation or 

other recovery action.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:19, F:0] + 24h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DS

31:0

00000000h

RW/1S

System software sets this bit for native command queuing 

commands prior to setting the PxCI.CI bit in the same command slot entry. This field is 

cleared via the Set Device Bits FIS.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:19, F:0] + 24h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CI