Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
1980
Datasheet
17.8.22
Port-Serial ATA Control (PxSCTL0)—Offset 12Ch
Access Method
Default: 00000000h
11:8
0h
RO
Interface Power Management (IPM): 
Indicates the current interface state 0h = 
Device not present or communication not established. 1h = Interface in active state. 2h 
= Interface in PARTIAL power management state. 6h = Interface in SLUMBER power 
management state. 8h = PHYSLP asserted. All other values reserved. This field reflects 
the interface power management state for both device and host initiated power 
management. Note: If an automatic partial to slumber transition occurs, PxSSTS.IPM 
shall reflect that the host has entered slumber (PxSSTS.IPM = 6h.)
7:4
0h
RO
Current Interface Speed (SPD): 
Indicates the negotiated interface communication 
speed. 0h = Device not present or communication not established. 1h = Generation 1 
communication rate negotiated. 2h = Generation 2 communication rate negotiated. 3h 
= Generation 3 communication rate negotiated. All other values reserved
3:0
0h
RO
Device Detection (DET): 
Indicates the interface device detection and Phy state. 0h = 
No device detected and Phy communication not established. 1h = Device presence 
detected but Phy communication not established. 3h = Device presence detected and 
Phy communication established. 4h = Phy in offline mode as a result of the interface 
being disabled or running in a BIST loopback mode. All other values reserved. Note that, 
while the true reset default value of this register is 0h, the value read from this register 
depends on drive presence and the point in time within the initialization process when 
the register is read. Note: The means by which the implementation determines device 
presence may be vendor specific. However, device presence shall always be indicated 
anytime a COMINIT signal is received.
Bit 
Range
Default & 
Access
Description
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
PxSCTL0: 
ABAR Type: 
PCI Configuration Register (Size: 32 bits)
ABAR Reference: 
[B:0, D:19, F:0] + 24h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RS
VD0
PM
P
SP
M
IP
M
SP
D
DE
T
Bit 
Range
Default & 
Access
Description
31:20
0b
RO
RSVD0: 
Reserved
19:16
0h
RW
Port Multiplier Port (PMP): 
This field is not used by AHCI.
15:12
0h
RW
Select Power Management (SPM): 
This field is not used by AHCI.
11:8
0h
RW
Interface Power Management Transitions Allowed (IPM): 
Indicates which power 
states the HBA is allowed to transition to. If an interface power management state is not 
allowed via this register field, the HBA will not initiate that state and the HBA will 
PMNAKP any request from the device to enter that state. 0h No interface restrictions 1h 
Transitions to the PARTIAL state disabled 2h Transitions to the SLUMBER state disabled 
3hTransitions to both PARTIAL and SLUMBER states disabled 4h Transitions to the 
DEVSLP power management state are disabled 5h Transitions to the Partial and DEVSLP 
power management states are disabled 6h Transitions to the Slumber and DEVSLP 
power management states are disabled 7h Transitions to the Partial, Slumber and 
DEVSLP power management states are disabled All other values reserved