Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2020
Datasheet
17.17.2
PCS_DWORD1 (pcs_dword1)—Offset 4h
Access Method
Default: 00600060h
Type:
Message Bus Register
(Size: 32 bits)
pcs_dword1:
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0
re
g_txfsm_4us_de
la
y_7_0
re
g_
so
ft
re
se
t_
en
ab
le
cr
i_rx
eb
_e
iosenable
cri_rx
di
gfilts
q
_e
nable
re
g_txfsm_de
la
y_o
vrd
re
g_txfsm_4us_de
la
y_11_8
reg_pclk_r
ate
_1_0
reg_r
ate
_1_0
reg_ph
ymode
_2_0
re
g_
m
od
eov
re
n
re
g
_
da
ta
width
so
ft_r
es
et_n
re
g_d
igin
elb
en
re
g_dig
ife
lbe
n
re
g_s
tr
ap
g
ro
up_o
vr
de
n
reg_y
an
k_tim
er_done_b_o
vrd
reg_y
ank_time
r_
d
one_b_o
vr
d_en
Bit
Range
Default &
Access
Description
31:24
0h
RW
reg_txfsm_4us_delay_7_0:
Override counter value for 4 us delay in txfsm lane reset
to txbiasen delay
23
0h
RW
reg_softreset_enable:
When '1' the soft_reset_n bit will contol the lane reset When
'0' the hardware reset will control the lane reset Note for DP: In addition to
soft_reset_n,which will reset both TX0 and TX 1 in the lane, the reg_tx1_soft_reset_n
bit can be used to reset only TX1 in the lane and reg_tx2_soft_reset_n bit can be used
to reset only TX2
22
1h
RW
cri_rxeb_eiosenable:
When 1 enables EIOS based Rx power down
21
1h
RW
cri_rxdigfiltsq_enable:
When 1 enables unsquelch based Rx power up in P0 or P0s
20
0h
RW
reg_txfsm_delay_ovrd:
Override enable bit for reg_txfsm_4us_delay
19:16
0h
RW
reg_txfsm_4us_delay_11_8:
Override counter value for 4 us delay in txfsm lane
reset to txbiasen delay
15:14
0h
RW
reg_pclk_rate_1_0:
Override for pclk_rate 00 = gen1 01 = gen2 10 = gen3 11 = GbE
13:12
0h
RW
reg_rate_1_0:
Override for i_rate 00 = gen1 01 = gen2 10 = gen3 11 = GbE
11:9
0h
RW
reg_phymode_2_0:
Override for PHY Mode Selection 000 = PCIE 001 = USB3 010 =
GbE 011 = SATA/SAPIS 100 = Display 101 = DMI 110 = CIO 111 =Reserved
8
0h
RW
reg_modeovren:
When asserted selects register override bits for phymode, datawidth
etc
7:6
1h
RW
reg_datawidth:
Override for Tx data interface width. 00 - Unused 01 - x8/x10 width
(default ) 10 - x16/x20 width 11 - x32/x40 width