Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2089
17.19.20 PCS_DWORD19 (pcs_dword19)—Offset 4Ch
Access Method
Default: 00004F10h
Bit
Range
Default &
Access
Description
31:27
0h
RW
reserved524:
reserved
26
0h
RW
reg_lrc_calcsonly:
Determines whether LRC ADC1/2 sequence will be bypassed when
crireset_l goes from asserted to de-asserted state 0: Full LRC sequence will run (both
ADC1/2 and calculations) 1: Do not run LRC ADC1/2. Only LRC calculations sequence
will run. It is expected that ADC1/2 config registers will be overridden with desired
values when using this mode
25:24
X
RO
adcout_9_8:
ADC Output Value2 Output of the ADC decimination filter; 2 upper bits
out of 10.
23:16
X
RO
adcout_7_0:
ADC Output Value1 Output of the ADC decimination filter; 8 lower bits
out of 10.
15:8
80h
RW
adc2_9_2:
LRC ADC2 Value Values in this register will be used by LRC_FSM to
compute and cancel out IR drop. If register is written prior to LRC cycle, values will be
overridden by FSM. If registers are written after LRC cycle, the original values are
overridden and the new values will be applicable and will be used for subsequent cycle.
7:0
80h
RW
adc1_9_2:
LRC ADC1 Value Values in this register will be used by LRC_FSM to
compute and cancel out IR drop. If register is written prior to LRC cycle, values will be
overridden by FSM. If registers are written after LRC cycle, the original values are
overridden and the new values will be applicable and will be used for subsequent cycle.
Type:
Message Bus Register
(Size: 32 bits)
pcs_dword19:
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 0 0 1 0 0 0 0
iam
p
0calco
de_7_
0
cal_nu
m
ca
l_
st
ar
t
ca
l_
ty
pe
cal_inv
ca
l_
rs
t
ca
lclkdivsel_1_
0
res
er
ved
52
5
calib_done
ca
l_fb_co
unt
adc
_
acctime_1_
0
adc_c
lksel_1_
0
adc
m
u
xsel_2_
0
adc
start
Bit
Range
Default &
Access
Description
31:24
0h
RW
iamp0calcode_7_0:
IREF Opamp Calibration Codes These bits are written by the
calibration state machine. Bit7 - Calibration enable that configures the target into a
calibration mode Bit6 - Calibration sign bit Bit[5:0] - Calibration magnitude [lyonel to
check bit7 functionality].
23:20
0h
RW
cal_num:
Calibration Number or Address numbers of cal targets or address for specific
cal target if cal_type = 1
19
0h
RW
cal_start:
Calibration Start This bit is used to start a Cal cycle vias IOSF-SB. The cal
cycle will follow the normal cal cycle as set by cal_num, cal_type, cal_inv and cal_rst.
The Cal cycle starts when this bit transitions 0 1 1 = Run Cal. 0 = wait (default)
18
0h
RW
cal_type:
Calibration Type Enable calibration of one cal target defined by cal_num 0 =
multi 1 = single