Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2094

Datasheet

16

1h

RW

1: The assertion of lane reset will have the effect of gating 

the susclk and de-asserting the internal laneclkreq. This mode is only valid when the 

data lane dynamic clock gating mode is set to a non-zero value (i.e. 01, 10, and 11). 0: 

The assertion of lane reset will have no effect on the gating of susclk and state of the 

internal laneclkreq signal.

15

1h

RW

Controls whether the internal laneclkreq will be forced to 1 or 0 

when cfg_data_dynclkgate_mode is set to 00 or 10. 1: force laneclkreq high 0: force 

laneclkreq low. This mode will likely be used when one of the lanes is disabled while 

other lanes in the family are enabled. In this case the internal laneclkreq of the disabled 

lane should be de-asserted (not influencing the clk gating decision)

14:10

10h

RW

This register will control the number of cycles to delay 

the susclk enable de-assertion, in addition to the de-assertion of the laneclkreq signal 

sent out of the datalane. The susclk enable must be continuously de-asserted for the 

duration of this delay in order for the de-asserted state to be captured by the clock 

gating controller. 5'b00000 - 0 Cycle Delay 5'b00001 - 1 Cycle Delay 5'b00010 - 2 Cycle 

Delay ................ 5'b11110 - 30 Cycle Delay 5'b11111 - 31 Cycle Delay

9:8

0h

RW

Controls the dynamic clock gating behavior in the 

data lane. 00 - susclk gating and laneclkreq disabled (Forced to configured value). In 

this mode the susclk will not be gated under any circumstances and the laneclkreq sent 

out of the lane will be forced to a programmed value (can be forced high or low) 01 - 

susclk gating disabled, laneclkreq enabled . In this mode the susclk will not be gated 

under any circumstances. The laneclkreq sent out of the data lane will toggle based on 

whether the lane power state, susclk need and the previous lane's laneclkreq signal. 10 

- susclk gating enabled, laneclkreq disabled (forced to configured value) - In this mode 

the susclk will be gated during P2/Slumber when there are no requests to change the 

TX common mode. The laneclkreq sent out of the lane will be forced to a programmed 

value (can be forced high or low) 11 - susclk gating and laneclkreq enabled - In this 

mode the susclk will be gated during P2/Slumber when there are no requests to change 

the TX common mode. The laneclkreq sent out of the data lane will toggle based on the 

lane power state, susclk need and the previous lane's laneclkreq signal.

7

0h

RW

EIOS Wait Time Override Enable for Rx Turn OFF 0: 

hardware value for EIOS wait timer is selected. 1: selects cri_eios_waittime[6:0]

6:0

20h

RW

EIOS Wait Time for Rx Turn OFF Represents override value 

timer in PCS that comes into play during EIOS based turn off Rx (Rx L0s) 0000000 - 

Timer is bypassed 0000001 - 1 PLL link clock period delay (2ns) 0000010 - 2 PLL link 

clock period delay (4ns) ... 0100000 - 32 PLL link clock periods delay (64ns) - default