Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2092
Datasheet
17.19.23 PCS_DWORD22 (pcs_dword22)—Offset 58h
Access Method
Default: 00000000h
17.19.24 PCS_DWORD23 (pcs_dword23)—Offset 5Ch
Access Method
Default: 00180888h
Type:
Message Bus Register
(Size: 32 bits)
pcs_dword22:
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
rxvgar
coffs
et
_7_0
rx
te
rm
rc
offs
et
_7_0
txr
coffs
et
_7_0
ir
ef
rc
offs
et
_7_0
Bit
Range
Default &
Access
Description
31:24
0h
RW
rxvgarcoffset_7_0:
Rx VGA Rcomp Offset Same description as IREF Rcomp Offset,
but applies to RxVGA Rcomp.
23:16
0h
RW
rxtermrcoffset_7_0:
Rx Termination Rcomp Offset Same description as IREF Rcomp
Offset, but applies to RxTerm Rcomp.
15:8
0h
RW
txrcoffset_7_0:
Tx Rcomp Offset Same description as IREF Rcomp Offset, but applies
to Tx Rcomp.
7:0
0h
RW
irefrcoffset_7_0:
Iref Rcomp Offset This value is added to the scaled LRC code to
determine the final calibration code used by the Iref block. 2's complement format. The
full 8-bit offset is used with the scale multiplier to determine the final 8-bit value, but
the Iref target only uses the upper MSBs of the final value. 0x00: Offset = 0 0x01:
Offset = +1 0x7F: Offset = +127 0xFF: Offset = -1 0x80: Offset = -128 Note: The final
rcomp code has rollover protection so the final rcomp code + offset will not exceed the
min/max range.
Type:
Message Bus Register
(Size: 32 bits)
pcs_dword23:
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0
iclkqcfg_spar
e_7_0
ic
lkicfg_s
pare_7
ic
lkicfg_spar
e_6_3
ic
lkicfg_spar
e_2_0
re
se
rv
ed
526
i_drvc
fg_3_0
i_ploadc
fg_3_0
ipbiasc
trl_3_0