Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2122
Datasheet
18.6.2
Device ID (DID)—Offset 2h
Access Method
Default: 8C31h
18.6.3
Command (CMD)—Offset 4h
Access Method
Default: 0000h
Type:
PCI Configuration Register
(Size: 16 bits)
Offset:
15
12
8
4
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
1
DID
Bit
Range
Default &
Access
Field Name (ID): Description
15:0
8C31h
RO/V
Device ID (DID):
See Global Device ID table in Chap. 6 for value
Power Well:
Core
Type:
PCI Configuration Register
(Size: 16 bits)
Offset:
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSV
D
ID
FBE
SE
R
R
WC
C
PE
R
VP
S
MWI
SC
E
BME
MSE
IOSE
Bit
Range
Default &
Access
Field Name (ID): Description
15:11
00h
RO
Reserved (RSVD):
Reserved.
Power Well:
Core
10
0b
RW
Interrupt Disable (ID):
When cleared to 0, the function is capable of generating
interrupts. When 1, the function can not generate its interrupt to the interrupt controller.
Note that the corresponding Interrupt Status bit is not affected by the interrupt enable.
Power Well:
Core
9
0b
RO
Fast Back to Back Enable (FBE):
Reserved.
Power Well:
Core
8
0b
RW
SERR# Enable (SERR):
When set to 1, the XHC is capable of generating (internally)
SERR#. See section on error handling.
Power Well:
Core
7
0b
RO
Wait Cycle Control (WCC):
Reserved.
Power Well:
Core