Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2301
18.7.163 USB2 Port Link Control 3 (USB2_LINK_MGR_CTRL_REG3)—
Offset 80F8h
This set of registers is used to control the USB set of timers. They are spread over 4
registers each 32 bits wide.
Access Method
Default: F865EB6Bh
18.7.164 USB2 Port Link Control 4 (USB2_LINK_MGR_CTRL_REG4)—
Offset 80FCh
This set of registers is used to control the USB set of timers. They are spread over 4
registers each 32 bits wide.
Access Method
4:0
00h
RW
FS/LS Mode SE0 Disconnect Delay[12:8] (FSLS_SE0_DIS_DEL_12_8):
# of
microseconds of SE0 in FS/LS mode to register disconnect had occurred.
Power Well:
SUS
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
1 1 1 1 1 0 0 0 0 1 1 0 0 1 0 1 1 1 1 0 1 0 1 1 0 1 1 0 1 0 1 1
U2_IG
N
_LS_DUR_3
_
0
U3_
IGN_LS
_
DU
R
TO
T_RST_DUR_15
_1
Bit
Range
Default &
Access
Field Name (ID): Description
31:28
Fh
RW
U2 Entry Ignore Linestate Changes Duration[3:0] (U2_IGN_LS_DUR_3_0):
# of
microseconds after entering U2, linestate changes are ignored as bus settles
Power Well:
SUS
27:15
10CBh
RW
U3 Entry Ignore Linestate Changes Duration (U3_IGN_LS_DUR):
# of
microseconds after entering U3, linestate changes are ignored as bus settles
Power Well:
SUS
14:0
6B6Bh
RW
Total Reset Duration[15:1] (TOT_RST_DUR_15_1):
# of microseconds for total
reset duration
Power Well:
SUS