Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2300
Datasheet
18.7.162 USB2 Port Link Control 2 (USB2_LINK_MGR_CTRL_REG2)—
Offset 80F4h
This set of registers is used to control the USB set of timers. They are spread over 4
registers each 32 bits wide.
Access Method
Default: 80C40620h
1
0b
RW
Force PHY Reset (FORCE_PHY_RST):
•
•
0 = Normal Operation (default)
•
1 = Force PHY Reset
Power Well:
SUS
0
0b
RW
USB2 Accelerated Simulation Timing (U2_ACC_SIM_TIM):
•
•
0 = Normal Operation (default - FPGA/ASIC)
•
1 = USB2 Accelerated Simulation Timing (default - simulation)
Power Well:
SUS
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0
TOT
_
R
S
T
_
D
U
R
_
0
CH
IRPK
_DU
R
K
J_
D
IS_CON_DEL
FSLS_SE
0_DIS_DE
L_12_
8
Bit
Range
Default &
Access
Field Name (ID): Description
31
1b
RW
Total Reset Duration[0] (TOT_RST_DUR_0):
# of microseconds for total reset
duration
Power Well:
SUS
30:18
0031h
RW
Chirp-K Duration (CHIRPK_DUR):
# of microseconds of Chirp-K to register that a
device is chirping
Power Well:
SUS
17:5
0031h
RW
K/J Disconnect Connect Delay (KJ_DIS_CON_DEL):
# of microseconds of K/J in
disconnected state to register connect has occurred.
Power Well:
SUS