Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2305
18.7.169 USB2 Linestate Debug (LINESTATE_DEBUG_REG)—Offset 8130h
Access Method
Default: 00000000h
23:12
647h
RW
HS Max BW Units (HS_MAX_BW):
Max. Number of BW units for HS ports.
(denominator in 80% calculation)
Power Well:
Core
11:0
F42h
RW
SS Max BW Units (SS_MAX_BW):
Max. Number of BW units for SS ports.
(denominator in 90% calculation)
Power Well:
Core
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSV
D
P14_UTMI_LS
P13_UTMI_LS
P12_UTMI_LS
P11_UTMI_LS
P10_UTMI_LS
P9_UTMI_LS
P8_UTMI_LS
P7_UTMI_LS
P6_UTMI_LS
P5_UTMI_LS
P4_UTMI_LS
P3_UTMI_LS
P2_UTMI_LS
P1_UTMI_LS
Bit
Range
Default &
Access
Field Name (ID): Description
31:28
0h
RO
RESERVED (RSVD):
Reserved.
Power Well:
Core
27:26
0h
RO
Port 14 UTMI Linestate (P14_UTMI_LS):
Reserved.
Power Well:
Core
25:24
0h
RO
Port 13 UTMI Linestate (P13_UTMI_LS):
Reserved.
Power Well:
Core
23:22
0h
RO
Port 12 UTMI Linestate (P12_UTMI_LS):
Reserved.
Power Well:
Core
21:20
0h
RO
Port 11 UTMI Linestate (P11_UTMI_LS):
Reserved.
Power Well:
Core
19:18
0h
RO
Port 10 UTMI Linestate (P10_UTMI_LS):
Reserved.
Power Well:
Core
17:16
0h
RO
Port 9 UTMI Linestate (P9_UTMI_LS):
Reserved.
Power Well:
Core